參數(shù)資料
型號: XRT71D03IVTR-F
廠商: Exar Corporation
文件頁數(shù): 5/24頁
文件大?。?/td> 0K
描述: IC JITTER ATTENUATOR 3CH 64TQFP
標準包裝: 1,000
類型: *
PLL:
輸入: 時鐘
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 3:2
差分 - 輸入:輸出: 無/無
頻率 - 最大: 44.736MHz
除法器/乘法器: 無/無
電源電壓: 3.135 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-TQFP(10x10)
包裝: 帶卷 (TR)
á
XRT71D03
3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR
REV. 1.2.0
12
SYSTEM DESCRIPTION
The XRT71D03 is an integrated 3-channel E3/DS3/
STS-1 jitter attenuator that attenuates the jitter from
the input clock and data. The jitter attenuation perfor-
mance meets the latest specifications such as Bellcore
GR-499 CORE,GR-253 CORE, ETSI TBR24,ITU-T
G.751,ITU-T G.752 and ITU-T G.755 standards.
In addition, the XRT71D03 also meets both the map-
ping and pointer adjustment jitter generation criteria
for both Category I and Category II interfaces as
specified in Bellcore GR-253.
The XRT71D03 also meets the DS3 wander specifi-
cation that apply to SONET and asynchronous inter-
faces as specified in the ANSI T1.105.03b 1997 stan-
dard.
Additionally, to support loop-timing applications, the
XRT71D03 can also be used to reduce and limit the
amount of jitter in the recovered line clock signal.
Figure 5 presents a simple block diagram of the
XRT71D03, when it is configured to operate in the
Hardware Mode and Figure 6 presents a simple block
diagram of the XRT71D03, when it is configured to
operate in the Host Mode.
FIGURE 5. ILLUSTRATION OF A TYPICAL CHANNEL_N OF THE XRT71D03 CONFIGURED TO OPERATE IN THE HARD-
WARE
MODE
FSS
HOST
Rest
DS3/E3_n
16/32 Bit FIFO
Timing Control Block /
Phase locked Loop
Write Clock
Read Clock
RRCLK_n
RRPOS_n
RRNEG_n
FL_n
DJA_n
RClk_n
RCLKES
RPOS_n
RNEG_n
ICT
MCLK_n
Jittery
Clock
Smoothed
Clock
RRCLKES
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