參數(shù)資料
型號: XRT71D03IVTR-F
廠商: Exar Corporation
文件頁數(shù): 14/24頁
文件大?。?/td> 0K
描述: IC JITTER ATTENUATOR 3CH 64TQFP
標準包裝: 1,000
類型: *
PLL:
輸入: 時鐘
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 3:2
差分 - 輸入:輸出: 無/無
頻率 - 最大: 44.736MHz
除法器/乘法器: 無/無
電源電壓: 3.135 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-TQFP(10x10)
包裝: 帶卷 (TR)
á
XRT71D03
3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR
REV. 1.2.0
20
the falling edge of SClk Cycle #8 (see Figure 11) the
serial data output signal (SDO) becomes active. At
this point the user can begin reading the data con-
tents of the addressed Command Register (at Ad-
dress [A4, A3, A2, A1, A0]) via the SDO output pin.
The Serial Interface will output this eight bit data word
(D0 through D7) in ascending order (with the LSB
first), on the falling edges of the SClk. The data (on
the SDO output pin) is stable for reading on the very
next rising edge of the SClk.
3.1.6
Write Operation
Once the last address bit (A4) has been clocked into
the SDI input, the Write operation will proceed
through an idle period, lasting three SClk periods. Pri-
or to the rising edge of SClk Cycle #9, the eight bit
data word is applied to SDI input. Data on SDI is
latched on the rising edge of SClk.
NOTES:
1. A5 is always “0”.
2. R/W = “1” for Read Operations
3. R/W = “0” for Write Operations
4. Denotes a “don’t care” value (shaded areas)
3.1.7
Simplified Interface Option
The user can simplify the design of the circuitry con-
necting to the Microprocessor Serial Interface by ty-
ing both the SDO and SDI pins together, and reading
data from and/or writing data to this combined signal.
This simplification is possible because only one of
FIGURE 11. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE
D0
D1
D2
D7
D6
D5
D4
D3
High Z
SDO
A0
D0
R/W
D1
A6
0
A4
A3
A2
A1
D7
D6
D5
D4
D3
D2
SDI
1234567
89
1 0
1 1
1 2
1 3
1 4
1 5
1 6
SClk
CS
High Z
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