PIN
參數(shù)資料
型號： XRT71D00IQTR-F
廠商： Exar Corporation
文件頁數(shù)： 21/26頁
文件大小： 0K
描述： IC JITTER ATTENUATOR SGL 32TQFP
標(biāo)準(zhǔn)包裝： 1,500
類型： *
PLL： 是
輸入： 時鐘
輸出： 時鐘
電路數(shù)： 1
比率 - 輸入:輸出： 3:2
差分 - 輸入:輸出： 無/無
頻率 - 最大： 44.736MHz
除法器/乘法器： 無/無
電源電壓： 3.135 V ~ 5.25 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-LQFP
供應(yīng)商設(shè)備封裝： 32-TQFP（7x7）
包裝： 帶卷 (TR)
XRT71D00
á
E3/DS3/STS-1 JITTER ATTENUATOR
REV. 1.2.0
3
PIN DESCRIPTIONS
PIN DESCRIPTION
PIN #NAME
TYPE
DESCRIPTION
1
NC
***
This pin is not connected internally
2
RNEG
I
Receive Negative Data (Jittery) Input
The input jittery negative data is sampled either on the rising or falling edge of RClk
depending on the setting of ClkES (pin 10). This data will ultimately be output via the
RRNEG output pin.
If ClkES is “high”, then RNEG will be sampled on the falling edge of RClk.
If ClkES is “l(fā)ow”, then RPOS will be sampled on the rising edge of RClk.
This pin is typically tied to the “RNEG” output pin of the LIU.
NOTES:
1. For “Jitter Attenuator” applications, this pin is typically connected to the
“RNEG” output pin of the corresponding LIU IC.
2. The user should tie this input pin to “GND” for “SONET De-Synchronization”
and “Single-Rail Jitter Attenuator” Applications.
3
RClk
I
Receive Clock (Jittery) Input
The user is expected to supply the “jittery” clock signal (e.g., the clock signal that needs
to be “smoothed”) to this input pin.
For Jitter Attenuation Applications:
The user should connect the “Recovered Line Clock” (RCLK) output signal (of the DS3,
E3 or STS-1 LIU IC) to this input pin.
For SONET De-synchronizer Applications:
The user should connect the “Receive DS3 Output” clock signal (of the OC-N to DS3
Mapper/De-Mapper IC) to this input pin.
The XRT71D00 device will use this clock signal to latch the data, residing on the
“RPOS” and “RNEG” input pins, into the chip.
If the “CLKES” input pin (or bit-field) is “high”, then the XRT71D00 device will sample
the data on the “RPOS” and “RNEG” input pins, on the falling edge of the “RCLK” clock
signal.
If the “CLKES” input pin (or bit-field) is “l(fā)ow”, then the XRT71D00 device will sample the
data on the “RPOS” and “RNEG” input pins, on the rising edge of the “RCLK” clock sig-
nal.
4
GND
***
Digital Ground
5
MClk
I
Master Clock Input.
This input pin functions as the reference clock for the internal PLL. The user is
expected to apply a 44.736MHz+/-20ppm (for DS3 applications), 34.368MHz+/-
20ppm (for E3 applications) or a 51.84MHz+/- 20ppm (for STS-1 applications) to this
input pin. This clock must be continuous and jitter free with duty cycle between 30 to
70%.
6
GND
***
Analog Ground
7
VDD
***
Analog Positive Supply: 3.3V or 5.0V ± 5%
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參數(shù)描述
XRT71D03 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR
XRT71D03ES 功能描述:時鐘合成器/抖動清除器 3CH T3/E3JA w/T73LC03A RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT71D03IV 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR
XRT71D03IV-F 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT71D03IVTR-F 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
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