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參數(shù)資料
| 型號： | XRT6164AIDTR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX DGTL INTERFACE 16SOIC |
| 產(chǎn)品變化通告： | Packaging Change 15/Jul/2010 |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
XRT6164A
6
Rev. 3.0.1
SYSTEMDESCRIPTION
The XRT6164A is a general purpose line
interface chip that contains the receive and
transmit circuitry necessary to convert TTL logic levels
to a CMOS signal both to and from a twisted pair cable.
Receiver
The XRT6164A receiver section converts a balanced
CMOS signal that has been attenuated and distorted
by up to 10dB of twisted pair cable to active-low TTL-
compatible logic levels.
The cable is transformer coupled to the receiver differ-
ential inputs (RX+IP, RX-IP) which are biased through
the input transformer secondary winding by a voltage
generated on-chip (I/P BIAS). The CMOS receive signal
is applied to a peak detector, and to a pair of data
comparators. The peak detector output voltage
charges an external capacitor connected to PEAK
CAP. This voltage generates a data comparator bias
level that is approximately 50% of the peak input pulse
amplitude.
Thus, data slicing is automatically accomplished at the
optimum level over the full cable loss range. TTL-
compatible output stages buffer the receiver digital
outputs (S+R, S-R) and provide active low signals
corresponding to received positive and negative input
pulses.
Loss of input signal is detected by a comparator that
monitors input signal level. An active-low TTL-compat-
ible logic level (RX ALARM) indicates signal loss.
Comparator hysteresis prevents chatter on this output.
Ping-pong operation is made possible by the time
compression multiplex control input (TCM CON). A
logic 0 applied to this pin during transmission stores
the peak detector output voltage by disconnecting the
peak detector storage capacitor charge and discharge
paths.
Since the receive data comparator bias voltage is
stored during transmit mode, it is immediately available
when receive mode resumes.
Transmitter
The XRT6164A transmitter section contains two
matched open collector output drivers that are capable
of driving the line transformer directly with a current up
to 40mA. The transmitter output drivers include diode
clamps to ensure non-saturating operation. Transmit-
ter digital inputs, which are active-low, are TTL-compat-
ible. External resistors are used between the transmit-
ter outputs and the output transformer primary to set
the output pulse amplitude.
APPLICATION INFORMATION
Figure 2 shows a general line driver application circuit
using the XRT6164A. This device converts CMOS
transmit and receive signals in the 64Kbps to
1.544Mbps range to active-low TTL-compatible logic
levels. CMOS signals that have been attenuated and
distorted by twisted pair cable are transformer-coupled
to the line side of the XRT6164A as shown on the left
side of Figure 2. Suggested transformers for both the
input and output applications are the Pulse types PE-
65535 or TTI-7147 for 64Kbps use and the PE-65835 for
1.544Mbps applications.
The right side of Figure 2 shows the TTL-compatible
digital inputs and outputs. Please refer to the pin
description section of this data sheet for detailed
information about each signal.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT6164AIP | 制造商:EXAR 制造商全稱:EXAR 功能描述:Digital Line Interface Transceiver |
| XR-T6164AIP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM Transceiver |
| XRT6164AIP-F | 功能描述:外圍驅(qū)動器與原件 - PCI codirectionalIntrfc RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT6164CD | 制造商:Exar Corporation 功能描述: |
| XR-T6164CD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM Transceiver |
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