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參數(shù)資料
| 型號(hào)： | XRT59L91ID-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 8/28頁 |
| 文件大小： | 0K |
| 描述： | IC LIU E1 SGL 3.3V 16SOIC |
| 產(chǎn)品變化通告： | Packaging Change 14/Jul/2010 |
| 標(biāo)準(zhǔn)包裝： | 48 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.46 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 管件 |
| 其它名稱： | 1016-1576-5 XRT59L91ID-F-ND |
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XRT59L91
16
Rev. 1.0.0
2.2
The “Receive Equalizer” Block
After the XRT59L91 device has received the incoming
line signal, via the RTIP and RRing input pins, the first
block that this signal will pass through is the Receive
Equalizer block.
As the line signal is transmitted from a given “Transmit-
ting” terminal, the pulse shapes (at that location) are
basically “square”. As this line signal travels from the
“transmitting terminal” (via the coaxial cable or twisted
pair) to the receiving terminal, it will be subjected to
“frequency-dependent” loss. In other words, the higher
frequency components of the signal will be subjected
to a greater amount of attenuation than will the lower
frequency components. If this line signal travels over
reasonably long cable lengths, then the shape of the
pulses (which were originally square) will be distorted
and cause inter-symbol interference to increase.
The purpose of this block is to equalize the incoming
distorted signal, due to cable loss. In essence, the
Receive Equalizer block accomplishes this by subject-
ing the received line signal to “frequency-dependent”
amplification (which attempts to counter the fre-
quency-dependent loss that the line signal has experi-
enced).
By doing this, the Receive Equalizer is
attempting to restore the shape of the line signal so that
the received data can be recovered reliably.
2.3
The “Peak Detector and Slicer Block
After the incoming line signal has passed through the
Receive Equalizer block, it will be routed to the “Slicer”
block. The purpose of the “Slicer” block is to quantify
a given bit-period (or symbol) within the incoming line
signal as either a “1” or a “0”.
2.4
The “LOS Detector” Block
The LOS Detector block, within the XRT59L91 was
specifically designed to comply with the “LOS Decla-
ration/Clearance” requirements per ITU-T G.775. As a
consequence, the XRT59L91 device will declare an
LOS Condition, (by driving the “RxLOS” output pin
“high”) if the received line signal amplitude drops to –
35dB or below. Further, the XRT59L91 device will clear
the LOS Condition if the signal amplitude rises back up
to –12dB or above. Figure 10 presents an illustration of
G.775 spec for declaring and clearing LOS.
0 dB
-6 dB
-9dB
-35dB
Maximum Cable Loss for E1
LOS Signal Must be Declared
LOS Signal Must be Cleared
LOS Signal may be Cleared or Declared
Figure 10. Illustration of G.775 Spec.
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| XRT59L91IDTR-F | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI SNGLCHANNELE1LIU RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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