參數(shù)資料
型號: XRT59L91ID-F
廠商: Exar Corporation
文件頁數(shù): 22/28頁
文件大?。?/td> 0K
描述: IC LIU E1 SGL 3.3V 16SOIC
產(chǎn)品變化通告: Packaging Change 14/Jul/2010
標準包裝: 48
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: E1
電源電壓: 3.13 V ~ 3.46 V
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 16-SOIC W
包裝: 管件
其它名稱: 1016-1576-5
XRT59L91ID-F-ND
XRT59L91
3
Rev. 1.0.0
PIN CONFIGURATION
1
9
8
16
Tx C lk
Tx P O S
T VSS
Tx N E G
LLoop
R Loop
RxP O S
RxN E G
RxL O S
TR in g
TV D D
TTIP
RV DD
RV S S
RRing
RT IP
PIN DESCRIPTION
Pin#
Symbol
Type
Description
1
TxClk
I
Transmitter Clock Input:
If the user operates the LIU in the “clocked” mode, then the “Transmit
Section” of the LIU will use the falling edge of this signal to sample the
data at the TxPOS and TxNEG input pins.
Note: If the user operates the LIU in the “clockless” mode, then the
Terminal Equipment should not apply a clock signal to this input pin.
2
TxPOS
I
Transmit – Positive Data Input:
The exact signal that should be applied to this input pin depends upon
whether the user intends to operate the “Transmit Section” (of the device)
in the “Clocked” or “Clockless” Mode.
Clocked Mode -
The Terminal Equipment should apply bit-wide NRZ pulses on this input
pin, whenever the Terminal Equipment needs to transmit a “positive-
polarity” pulse onto the line via TTIP and TRing output pins. The
XRT59L91 device will sample this input pin upon the falling edge of the
TCLK signal.
Clockless Mode -
The Terminal Equipment should apply RZ pulses to this input pin,
anytime the Terminal Equipment needs to transmit a “positive-polarity”
pulse onto the line via TTIP and TRing output pins.
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