參數(shù)資料
型號(hào): XRS10L120IV
廠商: EXAR CORP
元件分類(lèi): 數(shù)字信號(hào)處理外設(shè)
英文描述: SERIAL ATA II: 1:2 PORT MULTIPLIER
中文描述: DSP-MULTIPLIER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, LQFP-100
文件頁(yè)數(shù): 46/52頁(yè)
文件大小: 399K
代理商: XRS10L120IV
XRS10L120
PRELIMINARY
44
SERIAL ATA II: 1:2 PORT MULTIPLIER
REV. P1.0.1
0.0085
7:4
Reserved
RO
-
Reserved
3
p_dvc_prt_en
RW
0
1 = enable all port multiplier ports on reset
0 = otherwise
2
p_as_mon_d3
RW
1
Control bit that
1 = monitors for unaligned Dword primitives
(Device 3 link layer)
0 = otherwise
1
p_sd_disable_d3
RW
0
Programmable scrambler/de-scrambler disable
(Device 3 link layer)
1 = disable
0 = enable
0
p_rx_feclr_d3
RW
0
Programmable fifo error clear for transmit elastic fifo
(Device 3 link layer)
1 = clear sticky error
0 = otherwise
0.0086
7:6
Reserved
RO
-
Reserved
5:3
p_dvc1_wght[2:0]
RW
000
Device port 1 weight for weighted-round robin arbitra-
tion Valid values 1-7
2:0
p_dvc0_wght[2:0]
RW
000
Device port 0 weight for weighted-round robin arbitra-
tion Valid values 1-7
0.0087
7:6
Reserved
RO
-
Reserved
5:3
p_dvc3_wght[2:0]
RW
000
Device port 3 weight for weighted-round robin arbitra-
tion Valid values 1-7
2:0
p_dvc2_wght[2:0]
RW
000
Device port 2 weight for weighted-round robin arbitra-
tion Valid values 1-7
0.0088
7:0
p_intvl_val[7:0]
RW
0xB7
programmable communication interval value for hot
plug FSM Interval is 27.3us * count
0.0089
7
Reserved
RO
-
Reserved
6:3
p_msb_rscnt[3:0]
RW
1000
The 4 MSB’s of the 20 bit timeout value used to decide
how long the PM should wait before issuing a restart
2
p_dlock_err_clr
RW
0
1 = clear the stick deadlock error indicator
0 = otherwise
1
p_restart_pm_en
RW
1
1 = port multiplier will restart if it enters deadlock
0 = otherwise
0
p_pwrmng_on
RW
1
1 = power management turned on in port
0 = power management turned off in port
0.0090
7
Reserved
RO
-
Reserved
6:4
p_col_ad[2:0]
RW
000
Col address of the SRAM in test mode
3:0
p_row_ad[11:0]
RW
0x00
Row address of the SRAM in test mode
T
ABLE
15: SATA P
ORT
M
ULTIPLIER
R
EGISTERS
A
DDRESS
H
EX
B
IT
(
S
)
N
AME
RW
R
ESET
V
ALUE
D
ESCRIPTION
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