參數(shù)資料
型號： XRM48L950PGET
廠商： Texas Instruments
文件頁數(shù)： 158/176頁
文件大?。?/td> 0K
描述： MCU 16/32Bit FLASH 3MB 144LQFP
標準包裝： 1
系列： Hercules™ ARM® RM4x
應用： 工業(yè)安全，醫(yī)療
核心處理器： ARM? Cortex? - R4F
程序存儲器類型： 閃存（3MB）
控制器系列： RM4
RAM 容量： 256K x 8
接口： CAN，以太網(wǎng)，I²C，LIN，MibSPI，SCI，SPI，USB
輸入/輸出數(shù)： 64
電源電壓： 1.14 V ~ 3.6 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
包裝： 托盤
供應商設備封裝： 144-LQFP（20x20）
其它名稱： 296-29389
SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
4.10.2 Main Features of Flash Module
Support for multiple flash banks for program and/or data storage
Simultaneous read access on a bank while performing program or erase operation on any other bank
Integrated state machines to automate flash erase and program operations
Software interface for flash program and erase operations
Pipelined mode operation to improve instruction access interface bandwidth
Support for Single Error Correction Double Error Detection (SECDED) block inside Cortex-R4F CPU
–
Error address is captured for host system debugging
Support for a rich set of diagnostic features
4.10.3 ECC Protection for Flash Accesses
All accesses to the program flash memory are protected by Single Error Correction Double Error Detection
(SECDED) logic embedded inside the CPU. The flash module provides 8 bits of ECC code for 64 bits of
instructions or data fetched from the flash memory. The CPU calculates the expected ECC code based on
the 64 bits received and compares it with the ECC code returned by the flash module. A signle-bit error is
corrected and flagged by the CPU, while a multi-bit error is only flagged. The CPU signals an ECC error
via its Event bus. This signaling mechanism is not enabled by default and must be enabled by setting the
"X" bit of the Performance Monitor Control Register, c9.
MRC p15,#0,r1,c9,c12,#0
;Enabling Event monitor states
ORR r1, r1, #0x00000010
MCR p15,#0,r1,c9,c12,#0
;Set 4th bit (‘X’) of PMNC register
MRC p15,#0,r1,c9,c12,#0
The application must also explicitly enable the CPU's ECC checking for accesses on the CPU's ATCM
and BTCM interfaces. These are connected to the program flash and data RAM respectively. ECC
checking for these interfaces can be done by setting the B1TCMPCEN, B0TCMPCEN and ATCMPCEN
bits of the System Control coprocessor's Auxiliary Control Register, c1.
MRC p15, #0, r1, c1, c0, #1
ORR r1, r1, #0x0e000000
;Enable ECC checking for ATCM and BTCMs
DMB
MCR p15, #0, r1, c1, c0, #1
4.10.4 Flash Access Speeds
For information on flash memory access speeds and the relevant wait states required, refer to Section 3.4.
4.10.5 Flash Program and Erase Timings for Program Flash
Table 4-23. Timing Specifications for Program Flash
Parameter
MIN
NOM
MAX
Unit
tprog (144bit)
Wide Word (144bit) programming time
40
300
s
tprog (Total)
3MByte programming time(1)
-40°C to 105°C
32
s
0°C to 60°C, for first
8
16
s
25 cycles
terase
Sector/Bank erase time(2)
-40°C to 105°C
0.03
4
s
0°C to 60°C, for first
16
100
ms
25 cycles
twec
Write/erase cycles with 15 year Data Retention
-40°C to 105°C
1000
cycles
requirement
(1)
This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes
programming 144 bits at a time at the maximum specified operating frequency.
(2)
During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase
a sector.
82
System Information and Electrical Specifications
Copyright 2012–2013, Texas Instruments Incorporated
Product Folder Links: RM48L950 RM48L750 RM48L550
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