參數(shù)資料
型號: XRD98L62
廠商: Exar Corporation
英文描述: CCD Image Digitizers with CDA,PGS and 12-Bit A/D(CCD圖像數(shù)字轉(zhuǎn)換器(帶CDA,PGS和12位A/D轉(zhuǎn)換器))
中文描述: 與綜合發(fā)展區(qū),和12的PGS CCD圖像數(shù)字轉(zhuǎn)換器,位A / D(防治荒漠化公約圖像數(shù)字轉(zhuǎn)換器(帶地帶素類和12位的A / D轉(zhuǎn)換器))
文件頁數(shù): 27/37頁
文件大?。?/td> 394K
代理商: XRD98L62
27
Rev. P2.00
XRD98L62
Preliminary
Reset Reject
In the default state the reset reject switches (
φ
3)are
always ON, they are not clocked. The reset pulse of
each pixel is transmitted to the first stage of the PGA.
Depending on the PGA gain and the actual voltage
level of the reset pulse, this could cause the first stage
of the PGA to rail. During the Black Level sampling the
PGA should have enough time to recuperate, but as a
precaution we have included the Reset Reject option.
When RSTreject = 1, the reset reject switches are
turned OFF at the end of the SPIX pulse, and turned
ON again at the start of the SBLK pulse. This will
effectively reject the reset pulse and prevent it from
railing the PGA.
CCD Signal
SBLK
SPIX
ADCLK
Black Level
Video
Level
φ
2
DelayB[8:6]
Figure 15. Pixel Rate Clock Timing with SPIXopt=0 (Default)
CCD Signal
SBLK
SPIX
ADCLK
Black Level
Video
Level
φ
2
Figure 16. Pixel Rate Clock Timing with SPIXopt=1
相關(guān)PDF資料
PDF描述
XRDAN28 Frequency Response Effects of Overampling and Averaging on A/D Output Data
XRDAN29 Criteria for Accurate Sampling of Analog Signals
XRDAN30 CMOS Current Output D/A Converter Design Concepts for Wide Bandwidth Applications
XRK32308_07 3.3V ZERO DELAY BUFFER
XRK32308CD-1 3.3V ZERO DELAY BUFFER
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