參數(shù)資料
型號(hào)： XRD98L59AIG-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 6/37頁(yè)
文件大?。?/td> 0K
描述： IC CCD DIGITIZER 10BIT 28TSSOP
標(biāo)準(zhǔn)包裝： 47
位數(shù)： 10
通道數(shù)： 1
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 2.7 V ~ 3.6 V
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 管件
其它名稱： XRD98L59AIG-F-ND
XRD98L59
14
Rev. 2.00
RSTREJ reduces CCD reset noise by disconnecting the
input of the XRD98L59 from the CCD during the CCD
reset pulse. RSTREJ is an internally generated signal.
RSTREJ disconnects the input after the SPIX and before
the SBLK sampling events to reject CCD reset noise.
The RSTREJ switch is always closed (the input is always
connected) if D6=0 in the clock register (address 0011)
of the serial port.
For the timing example shown in Figure 6, SBLK high
samples the pixel black level. The actual hold point of
the pixel black level occurs after a delay of tBK. tBK is
the aperture delay of the SBLK timing signal.
The polarities of the SBLK and SPIX signals are indepen-
dently programmable via the serial port.
For the timing example shown in Figure 6, SPIX high
samples the pixel video level. The actual hold point of
the pixel video level occurs after a delay of tVD. tVD is
the aperture delay of the SPIX timing signal. The
polarity of the SPIX signal is serial port programmable.
The function of the CDS block, shown in Figure 7, is to
sense the voltage difference between the black level and
video level for each pixel. The CDS and PGA are fully
differential to reject common mode noise. The PGA
output is converted to a single ended signal, and then fed
to the ADC.
REF
IN (CDS non-inverting input) should be connected,
via a capacitor, to the CCD “Common” voltage. This is
typically CCD ground.
CCD
IN (CDS inverting input)
should be connected, via a capacitor, to the CCD output
signal. The external coupling capacitors on CCD
IN and
REF
IN should be of equal values to minimize gain errors
(typically 0.01
f +/-10%).
Figure 7. Block Diagram of the CDS, Reset Phase: RSTREJ Switch is Open
+
PGA1
-
Vbias1 ~0.8
External
Coupling
Capacitors
VBIAS2
CLAMP
φ1
Gain
Register
to ADC
C
D
GND
Vout
C1
C2
C3
+
PGA2
-
+
BUF
-
C4
φ2
RSTREJ
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