參數(shù)資料
型號(hào): XRD98L59AIG-F
廠商: Exar Corporation
文件頁數(shù): 36/37頁
文件大小: 0K
描述: IC CCD DIGITIZER 10BIT 28TSSOP
標(biāo)準(zhǔn)包裝: 47
位數(shù): 10
通道數(shù): 1
電壓 - 電源,模擬: 2.7 V ~ 3.6 V
電壓 - 電源,數(shù)字: 2.7 V ~ 3.6 V
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 管件
其它名稱: XRD98L59AIG-F-ND
XRD98L59
8
Rev. 2.00
SERIAL INTERFACE
The XRD98L59 uses a three wire serial interface (LOAD,
SDI & SCLK) to access the programmable features and
controls of the chip.The serial interface uses a 12-bit shift
register. The first 4 bits shifted in are the address bits, the
next 8 bits are the data bits. The address bits select
which of the internal registers will receive the 8 data bits.
There is no checking or read back of the address bits to
ensure a valid register is written to. If the address bits
select an undefined register, the data will be discarded.
SCLK
SDI
LOAD
Time
A 3
A 2
A 1
A 0
D7
D6
D5
D4
D3
D2
D1
D0
t1
t2
t12
t11
t
L1
t
L2
t
SCLK
t
set
t
hold
MSB
L S B
SERIAL PORT PROCEDURES
1)
Set LOAD pin low to enable shift register.
2)
Shift in 4 address bits (msb first), followed by
8 data bits (msb first).
3)
Set LOAD pin high to transfer data from the
shift register to the serial interface register
array.
For optimum image quality, do not run the serial port
during active video. Serial port clocking can couple into
the signal path and degrade accuracy. Also, do not
continuously run SCLK.
Reseting the XRD98L59 is recommended after initial
power-up. It is generally good practice to reset the
XRD98L59 because the serial data may be forced to an
unknown state during power supply cycling by the digital
ASIC.
Figure 3. Serial Interface Timing Diagram
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