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參數(shù)資料
| 型號： | XRD9836 |
| 廠商： | Exar Corporation |
| 英文描述： | 16-BIT PIXEL GAIN AFE |
| 中文描述： | 16位像素增益模擬前端 |
| 文件頁數(shù)： | 17/32頁 |
| 文件大?。?/td> | 696K |
| 代理商： | XRD9836 |
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XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
17
MICRO-CONTROLLER SERIAL PORT
FOR MODE CONTROL (USIO):
The uSIO is a bidirectional I/O port which is used for
configuring various operating modes as well as phase
aligning internal clocks (delay control). The serial port
can be used to program any of the registers listed in
the registers table. Note that SDIO is a bidirectional
pin used to read or write the XRD9836 internal regis-
ters. The R/W bit will define the direction of the bus
after Address bits. If R/W = 0, a write to the XRD9836
is performed. If R/W = 1, a read of the XRD9836’s in-
ternal registers is performed.
During a write operation there must be 18 positive
edges of SCLK between the fall of LOAD and the rise
of LOAD. If there are more or less than 18, the write
operation will not take place. For a write to the
XRD9836 the SDIO pin stays configured as an input
for entire 18 SCLK's before LOAD goes high. The E0
and E1 bits are dummy (unused) bits.
For a read of the XRD9836 internal registers (R/W=1)
the E0 and E1 are used as a transition time for the
SDIO pin going from an input to a output. During this
time SDIO pin is tri-stated. SDIO is an input while se-
rial port accepts the address of the register to be read
and during the E0 and E1 time period transitions to
an output for the read operation.
During a read operation the first 18 positive edges are
used. If there are less than 18, not all of the data will
be output. If there are more than 18, only the first 18
bits will be valid. The data becomes valid after the ris-
ing edge of SCLK.
F
IGURE
15. S
ERIAL
P
ORT
W
RITE
T
IMING
(R/W=0)
A3
A2
A1
A0
A4
D7
D6
D5
D4
D3
D2
D1
D0
D8
D9
R/W
E0
E1
msb
msb
lsb
lsb
LOAD
SCLK
SDIO
Tusp
Tuss
Tusls
Tuslh
Write
Register Address
Dummy
bits
Write Register Data
SDIO
configured
as
Input
Tush
F
IGURE
16. S
ERIAL
P
ORT
R
EAD
T
IMING
(R/W=1)
A3
A2
A1
A0
A4
D7
D6
D5
D4
D3
D2
D1
D0
D8
D9
R/W
E0
E1
msb
msb
lsb
lsb
LOAD
SCLK
SDIO
Tusp
Tuss
Tusdvd
Tusls
Tuslh
Read
Register Address
Dummy
bits
Read Register Data
SDIO
configured
as
Input
Tri-state
Output
Tush
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