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參數(shù)資料
| 型號(hào)： | XRD87L99AIQ |
| 廠商： | EXAR CORP |
| 元件分類： | ADC |
| 英文描述： | LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX |
| 中文描述： | 8-CH 10-BIT RESISTANCE LADDER ADC, PARALLEL ACCESS, PQFP44 |
| 封裝： | 10 X 10 MM, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 9/23頁 |
| 文件大?。?/td> | 414K |
| 代理商： | XRD87L99AIQ |
XRD87L99
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
xr
9
F
IGURE
3. XRD87L99 T
IMING
D
IAGRAM
THEORY OF OPERATION
1.0
The XRD87L99 converts analog voltages into 1024
digital codes by encoding the outputs of coarse and
fine comparators. Digital logic is used to generate the
overflow bit. The conversion is synchronous with the
clock and it is accomplished in 2 clock periods.
The reference resistance ladder is a series of resis-
tors. The fine comparators use a patented interpola-
tion circuit to generate the equivalent of 1024 evenly
spaced reference voltages between V
REF(-)
and
V
REF(+)
.
The clock signal generates the two internal phases,
φ
B (CLK high) and
φ
S (CLK low = sample) (See Fig-
ure 1). The rising edge of the CLK input marks the
end of the sampling phase (
φ
S). Internal delay of the
clock circuitry will delay the actual instant when
φ
S
ANALOG-TO-DIGITAL CONVERSION
disconnects the latches from the comparators. This
delay is called aperture delay (t
AP
).
The coarse comparators make the first pass conver-
sion and selects a ladder range for the fine compara-
tors. The fine comparators are connected to the se-
lected range during the next
φ
B phase.
F
IGURE
4. XRD87L99 C
OMPARATORS
A
IN
Sampling, Ladder Sampling, and Conversion
Timing
Figure 3 shows this relationship as a timing chart. A
IN
sampling, ladder sampling and output data relation-
ships are shown for the general case where the levels
which drive the ladder need to change for each sam-
pled A
IN
time point. The ladder is referenced for both
last A
IN
sample and next A
IN
sample at the same
time. If the ladder's levels change by more than 1
LSB, one of the samples must be discarded. Also
note that the clock low period for the discarded A
IN
can be reduced to the minimum t
S
time.
Auto
Balance
CLOCK
Data
Analog
Input
Sample
N-1
Sample
N
Sample
N+1
Auto
Balance
N-1
T
S
V
IH
V
IL
V
OH
V
OL
t
F
t
B
t
R
t
S
t
DL
t
HLD
t
AP
φ
S
B
φ
B
φ
S
φ
Latch
Ref
Ladder
COARSE COMPARATOR
S
S
B
B
φ
φ
φ
φ
Latch
Selected
Range
FINE COMPARATOR
VIN
VIN
VTAP
VTAP
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| XRD87L99AIQ-F | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| XRD9814 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3-Channel 14/16-Bit Linear CCD/CIS Sensor Signal Processors |
| XRD9814ACV | 制造商:EXAR 制造商全稱:EXAR 功能描述:3-Channel 14/16-Bit Linear CCD/CIS Sensor Signal Processors |
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| XRD9814BCV | 制造商:EXAR 制造商全稱:EXAR 功能描述:3-Channel 14/16-Bit Linear CCD/CIS Sensor Signal Processors |
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