參數(shù)資料
型號: XRD87L99AIQ
廠商: EXAR CORP
元件分類: ADC
英文描述: LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
中文描述: 8-CH 10-BIT RESISTANCE LADDER ADC, PARALLEL ACCESS, PQFP44
封裝: 10 X 10 MM, PLASTIC, QFP-44
文件頁數(shù): 7/23頁
文件大?。?/td> 414K
代理商: XRD87L99AIQ
XRD87L99
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
xr
7
N
OTES
:
1 Guaranteed. Not tested.
2 Tester measures code transition voltages by dithering the voltage of the analog input (V
IN
). The difference between
the measured code width and the ideal value (V
REF
/1024) is the DNL error. The INL error is the maximum distance
(in LSBs) from the best fit line to any transition voltage.
3 See V
IN
input equivalent circuit.
4 Clock specification to meet aperture specification (t
AP
). Actual rise/fall time can be less stringent with no loss of
accuracy.
5 Specified values guarantee functional device. Refer to other parameters for accuracy.
6 System can clock the XRD87L99 with any duty cycle as long as all timing conditions are met.
7 Input range where input is converted correctly into binary code. Input voltage outside specified range converts to
zero or full scale output.
8 DV
DD
and AV
DD
are connected through the silicon substrate. Connect together at the package.
S
PECIFICATIONS
ARE
SUBJECT
TO
CHANGE
WITHOUT
NOTICE
Clock to WR Hold Time
t
CLKH2
0
ns
Power Down Time
1
t
PD
300
ns
Power Up Time
1
t
PU
200
ns
Data Enable Delay
t
DEN
14
16
ns
Data High Z Delay
t
DHZ
4
6
ns
Pipeline Delay (Latency)
1.5
cycles
P
OWER
S
UPPLIES
8
Power Down (I
DD
)
I
PD-DD
0.01
0.10
mA
PD=High, CLK High or Low
Operating Voltage (AV
DD
, DV
DD
)
V
DD
2.7
3.0
3.6
V
Current (AV
DD
+ DV
DD
)
I
DD
7
10
mA
PD=Low (Normal Mode)
V
DD
=3 V
E
LECTRICAL
C
HARACTERISTICS
AV
DD
= DV
DD
= 3 V, F
S
= 2 MH
Z
(50% D
UTY
C
YCLE
), V
REF(+)
= 2.6, V
REF(-)
= AGND,
T
A
= 25
°
C,
UNLESS
OTHERWISE
SPECIFIED
P
ARAMETER
S
YMBOL
M
IN
T
YP
M
AX
U
NITS
T
EST
C
ONDITIONS
/C
OMMENTS
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