參數(shù)資料
型號(hào): XR88C681CJ-F
廠商: Exar Corporation
文件頁(yè)數(shù): 40/101頁(yè)
文件大?。?/td> 0K
描述: IC UART CMOS DUAL 44PLCC
標(biāo)準(zhǔn)包裝: 27
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 1 字節(jié),3 字節(jié)
電源電壓: 4.75 V ~ 5.25 V
帶并行端口:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
其它名稱: 1016-1327-5
XR88C681
43
Rev. 2.11
A0 - A15
D0 - D7
-INT
-NMI
-WAIT
-BUSRQ
-HALT
-RFSH
-BUSAK
-WR
-RD
-MREQ
-IORQ
-M1
-RESET
-INTA
-IOR
-IOW
-MEMR
-MEMW
GND
+5V
PHI
Clock input
Figure 18. Schematic of Z-80 CPU Module
Z-80 CPU Interrupt Servicing Capability
The Z-80 CPU contains two interrupt request pins: -NMI
and -INT. -NMI is the “Non-Maskable” interrupt request
input pin; and -INT is the “Maskable” interrupt request
input pin. For the sake of interfacing to the DUART, we are
only concerned with the -INT pin.
The Z-80 CPU can be configured to operate in one of
three different interrupt modes:
D
External Vectored
D
Direct
D
“Peripheral” Vectored
Each of these interrupt modes use the -INT pin of the Z-80
CPU and will be discussed in the following sections.
External Vectored Interrupt Processing (Interrupt
Mode 0)
The Z-80 P will operate in this interrupt mode if the “IM 0”
instruction has been executed. Whenever the -INT pin is
asserted by a peripheral device requesting an interrupt,
the CPU will complete its current instruction. After
completion of this instruction, the CPU module will assert
-
INTA (toggle “l(fā)ow”). -INTA is the active-low “Interrupt
Acknowledge” signal that the CPU module outputs in
order to initiate the process of interrupt servicing. When
the Z-80 CPU operates in the Interrupt Mode 0, it is
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