
XR88C681
/1
# $
C# , - + D (" % $ +(-
B( ( $
note that the applicable bits, within the ACR register, are shaded.
( +
( +% + (% %$ (
Table 23 Please
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BRG Set
Select
Counter/Timer Mode and Source
Delta IP3
Interrupt
Delta IP2
Interrupt
Delta IP1
Interrupt
Delta IP0
Interrupt
J
J
Table 7
J
J 7
J
J 7
J
J 7
J
J 7
Table 23. ACR- Auxiliary Control Register
(- #N>O
Note:
This“two-tiered”interruptenabling/disablingapproach,forthe“InputChangeofState”interruptallowstremendousflexibility
for the user. Setting or clearingthe bitsin ACR[3:0] allowsthe userto specifyexactly whichInput Portpins tobe enabled(or
disabled) for generating the “Input Port Change of State” interrupt. Setting or clearing IMR[7] allows the user to “globally”
enable or disable this interrupt.
(+ #,(($('('+ +
( (% !('$ C- + D
( + #, '(% % % + %
( (%
+"
%% C- + D (" , (
$(4
$(-
#," (
( (% --$
+( % + '-(- ( (
E.3 28 Pin Packaged DUARTs
= ( '3-$% ' ( & (
("#, +" &(+'(%
(
$(' ( (% ( (
F25 . 2! '3 # $ 5* 2!
'3 ( + '( *
F. OUTPUT PORT
'%(%% + = ( ,
, ' %$ % - %
'
%$ +
(&-(-+ $-(%%"
* $ " * $ %
-(%" , B %$ %% %(-%
, (% $(" (' % ( % (
( ( %'
((- $ %% %(-% &
'+(-(
,-(- , (% ( $(++ +
'( (%
&('
% , '('(& '%(%% + ,
$
-(% ," $
'% + , '% + '
% + , (%
(% %%
2!4
#+ ( ,N6O (% % -(' CD" (% ( % (
,6 ( (- -(' CD 9(3(%" (+ ( ,N6O (%
% -('CD" (%%%( ,6((- -('
CD
(- 3% -(-
( $$ (% '$
''(% (% + B ((- (%
" % (3 +
$$%% (--$
'$%4
2 , , *# $ 92
, , *#
invoking the “SET OUTPUT PORT BITS” command, the
user is setting the bits (to logic “1”) in the OPR
8"
(% '( %% ( %(-
'%$(-
, (%
-(' CDL $
'&
(%( % + ,(%$
(%( , 9(3(%" 92,
, *# '$ (% (3$"
%'(+($ (%"
(( , C'$D -(' CD 8"
'%$(- , (% %
-(' CD
%
% %
It is important to note that when
%+'((( ,"+(- ,
% ," (%
, (" +(- , (% -(' CD
CD
+"
% + '
(%+ , ' %$ '$($(($&
( (% % & $$%%(--$ C2 , ,
*#D '$ %
Table 1
(
''&(-