REV. 1.3.0 2-CH FULL-SPEED USB UART RX_FIFO_LOW_LATENCY register bit to force the V1412 to be in the low latency mode, or the user" />
參數(shù)資料
型號(hào): XR21V1412IL32-F
廠商: Exar Corporation
文件頁(yè)數(shù): 3/32頁(yè)
文件大?。?/td> 0K
描述: IC UART FIFO USB DUAL 32QFN
產(chǎn)品培訓(xùn)模塊: UART Product Overview
XR21V141x Full-Speed USB UART Family
特色產(chǎn)品: XR21V141x Full-Speed USB UART
標(biāo)準(zhǔn)包裝: 490
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 128 字節(jié),384 字節(jié)
規(guī)程: USB 2.0
電源電壓: 2.97 V ~ 3.63 V
帶自動(dòng)流量控制功能:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-QFN 裸露焊盤(5x5)
包裝: 托盤
配用: 1016-1301-ND - EVAL BOARD FOR XR21V1412IL
其它名稱: 1016-1302
XR21V1412
11
REV. 1.3.0
2-CH FULL-SPEED USB UART
RX_FIFO_LOW_LATENCY register bit to force the V1412 to be in the low latency mode, or the user may
manually set this bit. With the CDC-ACM driver, the low latency mode is automatically set whenever the baud
rate is set to a value of less than 46921 bps using the CDC_ACM_IF_SET_LINE_CODING command.
1.5.4
GPIO
Each UART has 6 GPIOs. By hardware default the GPIOs are configured as inputs but may be modified by a
custom driver. Additionally, there are several modes that can be enabled to add additional feature such as
auto RTS/CTS flow control, auto DTR/DSR flow control or auto RS-485 half duplex control. See Table 14.
1.5.5
Automatic RTS/CTS Hardware Flow Control
GPIO5 and GPIO4 of the UART channel can be enabled as the RTS# and CTS# signals for Auto RTS/CTS
flow control when GPIO_MODE[2:0] = ’001’ and FLOW_CONTROL[2:0] = ’001’. Automatic RTS flow control is
used to prevent data overrun errors in local RX FIFO by de-asserting the RTS signal to the remote UART.
When there is room in the RX FIFO, the RTS pin will be re-asserted. Automatic CTS flow control is used to
prevent data overrun to the remote RX FIFO. The CTS# input is monitored to suspend/restart the local
transmitter (see Figure 5):
1.5.6
Automatic DTR/DSR Hardware Flow Control
Auto DTR/DSR hardware flow control behaves the same as the Auto RTS/CTS hardware flow control
described above except that it uses the DTR# and DSR# signals.
For Auto hardware flow control,
FLOW_CONTROL[2:0] = ’001’.
GPIO3 and GPIO2 become DTR# and DSR#, respectively, when
GPIO_MODE[2:0] = ’010’.
FIGURE 5. AUTO RTS AND CTS FLOW CONTROL OPERATION
T r a n s m it t e r
A u t o C T S
M o n i t o r
R e c e i v e r F I F O
T r ig g e r R e a c h e d
A u t o R T S
T r i g g e r L e v e l
R e m o t e U A R T
U A R T B
R T S A #
C T S B #
T X B
R X A
O N
O F F
O N
O F F
1
2
3
4
1 )
C O M p o r t o p e n e d , R X F I F O e m p t y , R T S A # o u t p u t i s a s s e r t e d
2 )
S i g n a l p r o p a g a t e d t o C T S B # i n p u t
3 )
D a t a b y t e s e n t e r T X F I F O , b e g i n t r a n s m it t i n g o n T X B
4 )
D a t a p r o p a g a t e s t o R e c e iv in g d e v i c e R X A
5 )
R X F I F O r e a c h e s t h r e s h o l d
6 )
R T S A # d e - a s s e r t s
7 )
S i g n a l p r o p a g a t e s t o C T S B # i n p u t
8 )
T r a n s m i s s io n s t o p s o n T X B
9 )
U S B B u l k - I n e m p t i e s R X F I F O b e lo w t h r e s h o l d , R T S A # i s a s s e r t e d
1 0 ) S i g n a l p r o p a g a t e d t o C T S B # in p u t
1 1 ) D a t a b y t e s r e s u m e t r a n s m i t t i n g o n T X B
5
6
7
8
9
1 0
1 1
R T S A #
C T S B #
T X B
R X A
C T S A #
T X A
R T S B #
R X B
R e c e iv e r F I F O
T r i g g e r R e a c h e d
A u t o R T S
T r i g g e r L e v e l
T r a n s m it t e r
A u t o C T S
M o n i t o r
L o c a l U A R T
U A R T A
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