REV. 1.3.0 CUSTOM[1]: Max Packet Size Logic 0 = bMaxPacketSize =" />
參數(shù)資料
型號: XR21V1412IL32-F
廠商: Exar Corporation
文件頁數(shù): 19/32頁
文件大小: 0K
描述: IC UART FIFO USB DUAL 32QFN
產品培訓模塊: UART Product Overview
XR21V141x Full-Speed USB UART Family
特色產品: XR21V141x Full-Speed USB UART
標準包裝: 490
特點: *
通道數(shù): 2,DUART
FIFO's: 128 字節(jié),384 字節(jié)
規(guī)程: USB 2.0
電源電壓: 2.97 V ~ 3.63 V
帶自動流量控制功能:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應商設備封裝: 32-QFN 裸露焊盤(5x5)
包裝: 托盤
配用: 1016-1301-ND - EVAL BOARD FOR XR21V1412IL
其它名稱: 1016-1302
XR21V1412
26
2-CH FULL-SPEED USB UART
REV. 1.3.0
CUSTOM[1]: Max Packet Size
Logic 0 = bMaxPacketSize = 64 bytes
Logic 1 = bMaxPacketSize = 63 bytes (this bit is automatically set to ’1’ if the XR21V1412 receives a
CDC_ACM USB command)
CUSTOM[7:2]: Reserved
These bits are reserved and should remain ’0’.
3.4.2
LOW_LATENCY Register Description - Chan A / B (Read/Write)
This register is automatically set to logic ’1’ for baud rates below 46921 bps, and can be manually set for baud
rates of 46921 bps and higher. This register enables the Low latency feature of the UART. Write to this
register following any desired baud rate setting change.
LOW_LATENCY[0]: Enable Low Latency mode
Logic 0 = Receive data is not forwarded from the Rx FIFO until bMaxPacketSize (64 bytes) or timeout (3
characters) has occurred.
Logic 1 = All data in the RX FIFO is provided to the USB host at the next BULK IN request irrespective of the
number of bytes in the FIFO.
LOW_LATENCY[7:1]: Reserved
These bits are reserved and should remain ’0’.
3.4.3
CUSTOM_INT_PACKET - Chan A / B (Read/Write)
This register is used to enable / disable GPIO status in the high data byte of the custom interrupt packet. See
Table 16, “Interrupt Packet Format,” on page 27 and Table 18, “Data Field of Customized Interrupt
Packet - Exar Vendor Specific,” on page 28.
CUSTOM_INT_PACKET[0]: GPIO1
Logic 0 = Disable GPIO1 status in custom interrupt packet.
Logic 1 = Enable GPIO1 status in custom interrupt packet.
CUSTOM_INT_PACKET[1]: GPIO2
Logic 0 = Disable GPIO2 status in custom interrupt packet.
Logic 1 = Enable GPIO2 status in custom interrupt packet.
CUSTOM_INT_PACKET[2]: Reserved
This bit is reserved and should remain ’0’.
CUSTOM_INT_PACKET[3]: GPIO0
Logic 0 = Disable GPIO0 status in custom interrupt packet.
Logic 1 = Enable GPIO0 status in custom interrupt packet.
CUSTOM_INT_PACKET[4]: GPIO3
Logic 0 = Disable GPIO3 status in custom interrupt packet.
Logic 1 = Enable GPIO3 status in custom interrupt packet.
CUSTOM_INT_PACKET[5]: GPIO4
Logic 0 = Disable GPIO4 status in custom interrupt packet.
Logic 1 = Enable GPIO4 status in custom interrupt packet.
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