REV. 1.3.0 2-CH FULL-SPEED USB UART LOOPBACK_CTL[2]: Enable Logic 0 = Internal UART (TX " />
參數(shù)資料
型號(hào): XR21V1412IL-0A-EB
廠商: Exar Corporation
文件頁(yè)數(shù): 16/32頁(yè)
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR21V1412IL
產(chǎn)品培訓(xùn)模塊: UART Product Overview
XR21V141x Full-Speed USB UART Family
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,USB 2.0 至 UART
嵌入式:
已用 IC / 零件: XR21V1412IL
已供物品:
相關(guān)產(chǎn)品: XR21V1412IL32TR-F-ND - IC USB UART FIFO FULL SPD 32QFN
1016-1302-ND - IC UART FIFO USB DUAL 32QFN
其它名稱(chēng): 1016-1301
XR21V1412
23
REV. 1.3.0
2-CH FULL-SPEED USB UART
LOOPBACK_CTL[2]: Enable
Logic 0 = Internal UART (TX to RX) loopback is disabled.
Logic 1 = Internal UART (TX to RX) loopback is enabled for channel selected by LOOPBACK_CTL[0]
LOOPBACK_CTL[7:3]: Reserved
These bits are reserved and should remain ’0’.
3.3.9
ERROR_STATUS Register Description - Read-only
This register reports any errors that may have occurred on the line such as framing, parity and overrun as well
as break status.
ERROR_STATUS[2:0]: Reserved
These bits are reserved. Any values read from these bits should be ignored.
ERROR_STATUS[3]: Break status
Logic 0 = No break condition
Logic 1 = A break condition has been detected (clears after read).
ERROR_STATUS[4]: Framing Error
Logic 0 = No framing error
Logic 1 = A framing error has been detected (clears after read). A framing error occurs when a stop bit is not
present when it is expected.
ERROR_STATUS[5]: Parity Error
Logic 0 = No parity error
Logic 1 = A parity error has been detected (clears after read).
ERROR_STATUS[6]: Overrun Error
Logic 0 = No overrun error
Logic 1 = An overrun error has been detected (clears after read). An overrun error occurs when the RX FIFO
is full and another byte of data is received.
ERROR_STATUS[7]: Break Status
Logic 0 = Break condition is no longer present.
Logic 1 = Break condition is currently being detected.
3.3.10
TX_BREAK Register Description (Read/Write)
Writing a non-zero value to this register causes a break condition to be generated continuously until the
register is cleared. If data is being shifted out of the TX pin, the data will be completely shifted out before the
break condition is generated.
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