REV. 1.4.0 3.3.12 GPIO_MODE Register Description (Read/Write) GPIO_MODE[2:0]: GPIO Mode Select
參數(shù)資料
型號: XR21V1410IL16-F
廠商: Exar Corporation
文件頁數(shù): 15/30頁
文件大?。?/td> 0K
描述: IC UART FIFO USB SGL 16QFN
產(chǎn)品培訓(xùn)模塊: UART Product Overview
XR21V141x Full-Speed USB UART Family
產(chǎn)品變化通告: XR21V1410IL16-F Packing Change 26/Jan/2011
特色產(chǎn)品: XR21V141x Full-Speed USB UART
標(biāo)準(zhǔn)包裝: 490
特點(diǎn): *
通道數(shù): 1,UART
FIFO's: 128 字節(jié),384 字節(jié)
規(guī)程: USB 2.0
電源電壓: 2.97 V ~ 3.63 V
帶自動流量控制功能:
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-QFN-EP(3x3)
包裝: 散裝
配用: 1016-1299-ND - EVAL BOARD FOR XR21V1410IL
其它名稱: 1016-1300
XR21V1410
22
1-CH FULL-SPEED USB UART
REV. 1.4.0
3.3.12
GPIO_MODE Register Description (Read/Write)
GPIO_MODE[2:0]: GPIO Mode Select
There are 4 modes of operation for the GPIOs. The descriptions can be found in “Section 1.5, UART” on
page 7.
GPIO_MODE[3]: RS485 Polarity
Logic 0 = GPIO5/RTS#/RS485 Low for TX
Logic 1 = GPIO5/RTS#/RS485 High for TX
GPIO_MODE[7:4]: Reserved
These register bits are reserved. When writing to these bits, the value should be ’0’. When reading from these
bits, they are undefined and should be ignored.
3.3.13
GPIO_DIRECTION Register Description (Read/Write)
This register controls the direction of pins configured as GPIO. (Pins configured for UART functions via the
GPIO_MODE register, e.g. RTS# are not controlled or reported in the GPIO_DIRECTION register.)
GPIO_DIRECTION[5:0]: GPIOx Direction
Logic 0 = GPIOx is an input.
Logic 1 = GPIOx is an output.
GPIO_DIRECTION[7:6]: Reserved
These register bits are reserved and should be ’0’.
3.3.14
GPIO_INT_MASK Register Description (Read/Write)
Enables / disables generation of a USB interrupt packet at the change of state of GPIO pins when they are
configured as inputs.
GPIO_INT_MASK[5:0]: GPIOx Interrupt Mask
Logic 0 = A change on this input causes the device to generate an interrupt packet.
Logic 1 = A change on this input does not cause the device to generate an interrupt packet.
GPIO_INT_MASK[7:6]: Reserved
These register bits are reserved and should be ’0’.
TABLE 14: GPIO MODES
BITS
[2:0]
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
MODE DESCRIPTION
000
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO Mode, All GPIO pins available as GPIO
001
GPIO0
GPIO1
GPIO2
GPIO3
CTS#
RTS#
GPIO4 and GPIO5 used for Auto RTS/CTS HW
Flow Control
010
GPIO0
GPIO1
DSR#
DTR#
GPIO4
GPIO5
GPIO2 and GPIO3 used for Auto DTR/DSR HW
Flow Control
011
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
RS485
GPIO5 used for auto RS-485 half-duplex control
100
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
RS485
GPIO5 used for auto RS-485 half-duplex control
after address match (See FLOW_CONTROL
mode 4).
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