REV. 1.4.0 1-CH FULL-SPEED USB UART 3.3.9 ERROR_STATUS Register Description - Read-only This register reports any errors that may " />
參數(shù)資料
型號(hào): XR21V1410IL16-F
廠商: Exar Corporation
文件頁數(shù): 14/30頁
文件大?。?/td> 0K
描述: IC UART FIFO USB SGL 16QFN
產(chǎn)品培訓(xùn)模塊: UART Product Overview
XR21V141x Full-Speed USB UART Family
產(chǎn)品變化通告: XR21V1410IL16-F Packing Change 26/Jan/2011
特色產(chǎn)品: XR21V141x Full-Speed USB UART
標(biāo)準(zhǔn)包裝: 490
特點(diǎn): *
通道數(shù): 1,UART
FIFO's: 128 字節(jié),384 字節(jié)
規(guī)程: USB 2.0
電源電壓: 2.97 V ~ 3.63 V
帶自動(dòng)流量控制功能:
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-QFN-EP(3x3)
包裝: 散裝
配用: 1016-1299-ND - EVAL BOARD FOR XR21V1410IL
其它名稱: 1016-1300
XR21V1410
21
REV. 1.4.0
1-CH FULL-SPEED USB UART
3.3.9
ERROR_STATUS Register Description - Read-only
This register reports any errors that may have occurred on the line such as framing, parity and overrun as well
as break status.
ERROR_STATUS[2:0]: Reserved
These bits are reserved. Any values read from these bits should be ignored.
ERROR_STATUS[3]: Break status
Logic 0 = No break condition
Logic 1 = A break condition has been detected (clears after read).
ERROR_STATUS[4]: Framing Error
Logic 0 = No framing error
Logic 1 = A framing error has been detected (clears after read). A framing error occurs when a stop bit is not
present when it is expected.
ERROR_STATUS[5]: Parity Error
Logic 0 = No parity error
Logic 1 = A parity error has been detected (clears after read).
ERROR_STATUS[6]: Overrun Error
Logic 0 = No overrun error
Logic 1 = An overrun error has been detected (clears after read). An overrun error occurs when the RX FIFO
is full and another byte of data is received.
ERROR_STATUS[7]: Break Status
Logic 0 = Break condition is no longer present.
Logic 1 = Break condition is currently being detected.
3.3.10
TX_BREAK Register Description (Read/Write)
Writing a non-zero value to this register causes a break condition to be generated continuously until the
register is cleared. If data is being shifted out of the TX pin, the data will be completely shifted out before the
break condition is generated.
3.3.11
RS485_DELAY Register Description (Read/Write)
RS485_DELAY[3:0]: Turn-around delay
This is the number of bit times the V1410 waits before de-asserting the GPIO5/RTS#/RS485 pin when it is
configured for automatic RS-485 half-duplex control.
RS485_DELAY[7:4]: Reserved
These bits are reserved and should be ’0’.
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