REV. 1.0.2 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER 3.0 UART INTERNAL REGISTERS The complete register set " />
參數(shù)資料
型號： XR20V2172L64-0B-EB
廠商： Exar Corporation
文件頁數(shù)： 14/51頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR20V2170 64QFN
標(biāo)準(zhǔn)包裝： 1
系列： *
XR20V2172
21
REV. 1.0.2
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
3.0 UART INTERNAL REGISTERS
The complete register set is shown below in Table 7 and Table 8.
TABLE 7: UART INTERNAL REGISTER ADDRESSES
ADDRESS
REGISTER
READ/WRITE
COMMENTS
16C550 COMPATIBLE REGISTERS
0X00
RHR - Receive Holding Register
THR - Transmit Holding Register
Read-only
Write-only
LCR[7] = 0
0X00
DLL - Divisor LSB
Read/Write
LCR[7] = 1, LCR
≠ 0xBF
0X01
DLM - Divisor MSB
Read/Write
0X02
DLD - Divisor Fractional
Read/Write
LCR[7] = 1, LCR
≠ 0xBF,
EFR[4] = 1
0X01
IER - Interrupt Enable Register
Read/Write
LCR[7] = 0
0X02
ISR - Interrupt Status Register
FCR - FIFO Control Register
Read-only
Write-only
0X03
LCR - Line Control Register
Read/Write
0X04
MCR - Modem Control Register
Read/Write
LCR
≠ 0xBF
0X05
LSR - Line Status Register
Read-only
0X06
MSR - Modem Status Register
Read-only
See
0X07
SPR - Scratch Pad Register
Read/Write
See
0X06
TCR - Transmission Control Register
Read/Write
See
0X07
TLR - Trigger Level Register
Read/Write
See
0X08
TXLVL - Transmit FIFO Level
Read-only
LCR[7] = 0
0x09
RXLVL - Receive FIFO Level
Read-only
0x0A
IODir - GPIO Direction Control Register
Read/Write
0x0B
IOState - GPIO State Register
Read/Write
0x0C
IOIntEna - GPIO Interrupt Enable Register
Read/Write
0x0D
Reserved
-
0x0E
IOControl - GPIO Control Register
Read/Write
0x0F
EFCR - Extra Features Control Register
Read/Write
0x02
EFR - Enhanced Function Register
Read/Write
LCR = 0xBF
0x04
Xon-1 - Xon Character 1
Read/Write
0x05
Xon-2 - Xon Character 2
Read/Write
0x06
Xoff-1 - Xoff Character 1
Read/Write
0x07
Xoff-2 - Xoff Character 2
Read/Write
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