REV. 1.0.2 2.17 Internal Loopback The V2172 UART pr" />
參數(shù)資料
型號(hào)： XR20V2172L64-0B-EB
廠商： Exar Corporation
文件頁數(shù)： 13/51頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR20V2170 64QFN
標(biāo)準(zhǔn)包裝： 1
系列： *
XR20V2172
20
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. 1.0.2
2.17
Internal Loopback
The V2172 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 14 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX, RTS# and DTR# pins are held while the CTS#, DSR# CD# and RI# inputs are ignored.
Caution: the RX input pin must be held HIGH during loopback test else upon exiting the loopback test the
UART may detect and report a false “break” signal. Also, auto RTS/CTS flow control is not supported during
internal loopback.
FIGURE 14. INTERNAL LOOP BACK
TX
RX
M
ode
m
/
General
Purpos
e
C
ontrol
Logic
In
ternal
Data
Bus
Li
ne
sa
n
d
Co
ntro
lSi
gn
als
RTS#
MCR bit-4=1
VCC
Transmit Shift Register
(THR/FIFO)
Receive Shift Register
(RHR/FIFO)
CTS#
DTR#
DSR#
RI#
CD#
OP1#
RTS#
CTS#
DTR#
DSR#
RI#
CD#
VCC
OP2#
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