參數(shù)資料
型號(hào): XR20M1172G28-0B-EB
廠商: Exar Corporation
文件頁數(shù): 26/55頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR20M1172 28TSSOP
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,UART
嵌入式:
已用 IC / 零件: XR20M1172
主要屬性: 2 通道
次要屬性: I²C & SPI 接口
已供物品:
其它名稱: 1016-1623
XR20M1172G28-0B-EB-ND
XR20M1172
32
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
REV. 1.2.0
4.6
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 11 for parity selection summary below.
Logic 0 = No parity.
Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR bit-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
BIT-1
BIT-0
WORD LENGTH
0
5
0
1
6 (default)
1
0
7
1
8
BIT-2
WORD
LENGTH
STOP BIT LENGTH
(BIT TIME(S))
0
5,6,7,8
1
5
1-1/2
1
6,7,8
2 (default)
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