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參數(shù)資料
| 型號： | XR19L200IL32-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 39/40頁 |
| 文件大小： | 0K |
| 描述： | IC UART/TXRX RS232 32QFN |
| 標準包裝： | 490 |
| 特點： | * |
| 通道數(shù)： | 1，UART |
| FIFO's： | 16 字節(jié) |
| 規(guī)程： | RS232 |
| 電源電壓： | 3 V ~ 5.5 V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調制解調器控制功能： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 32-QFN 裸露焊盤（5x5） |
| 包裝： | 托盤 |
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XR19L200
8
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.2
2.8
Crystal or External Clock Input
The L200 includes an on-chip oscillator (XTAL1 and XTAL2) to generate a clock when a crystal is connected
between the XTAL1 and XTAL2 pins of the device. Alternatively, an external clock can be supplied through the
XTAL1 pin. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock input and XTAL2 pin is the bufferred output which can be used as a clock signal for
other devices in the system. Please note that the input XTAL1 is not 5V tolerant and therefore, the maximum
voltage at the pin should be VCC when an external clock is supplied. For programming details, see
“Programmable Baud Rate Generator.”
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins. When VCC = 5V, the on-chip oscillator
can operate with a crystal whose frequency is not greater than 24 MHz. On the other hand, the L200 can
accept an external clock of up to 50MHz at XTAL1 pin also. Although the L200 can accept an exteran clock of
up to 50MHz, the maximum data rate supported by the RS-232 drivers is 250Kbps. For further reading on the
oscillator circuit please see the Application Note DAN108 on the EXAR web site at http://www.exar.com.
2.9
Programmable Baud Rate Generator
The L200 UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by a
software bit (bit-7) in the MCR register. This bit selects the prescaler to divide the input crystal or external clock
by a factor of 1 or 4. The clock output of the prescaler goes to the BRG. The BRG further divides this clock by
a programmable divisor (via DLL and DLM registers) between 1 and (216 -1) to obtain a 16X sampling rate
clock of the serial data rate. The sampling rate clock is used by the transmitter for data bit shifting and receiver
for data sampling. The BRG divisor defaults to the maximum baud rate (DLL = 0x01 and DLM = 0x00) upon
power up.
TABLE 2: INT (IRQ#) PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
INT Pin
(I/M# = 1)
0 = no data
1 = 1 byte
0 = FIFO below trigger level
1 = FIFO above trigger level
IRQ# Pin
(I/M# = 0)
1 = no data
0 = 1 byte
1 = FIFO below trigger level
0 = FIFO above trigger level
FIGURE 4. TYPICAL CRYSTAL CONNECTIONS
C1
22-47pF
C2
22-47pF
Y1
1.8432 MHz
to
24 MHz
R1
0-120
(Optional)
R2
500K - 1M
XTAL1
XTAL2
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