REV. 1.0.4 3.7 Receiver The receiver section contains an 8-bit Receive Shift " />
參數(shù)資料
型號(hào)： XR17V358IB176-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 41/68頁(yè)
文件大?。?/td> 0K
描述： IC UART PCIE OCTAL 176FPBGA
產(chǎn)品培訓(xùn)模塊： PCIe UARTs
UART Product Overview
標(biāo)準(zhǔn)包裝： 160
特點(diǎn)： *
通道數(shù)： 1，UART
FIFO's： 256 字節(jié)
規(guī)程： RS485
電源電壓： 1.2V，3.3V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類(lèi)型： 表面貼裝
封裝/外殼： 176-LFBGA
供應(yīng)商設(shè)備封裝： 176-FPBGA（13x13）
包裝： 托盤(pán)
配用： 1016-1296-ND - EVAL BOARD FOR XR17V358-E8
1016-1295-ND - EVAL BOARD FOR XR17V358-E4
1016-1293-ND - EVAL BOARD FOR XR17V358
其它名稱(chēng)： 1016-1294
XR17V358
46
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
REV. 1.0.4
3.7
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and Receive Holding Register (RHR). The
RSR uses the 16X, 8X or 4X clock for timing. It verifies and validates every bit on the incoming character in the
middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts
counting at the 16X, 8X or 4X clock rate. After 8 or 4 or 2 clocks the start bit period should be at the center of
the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in
this manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are
sampled and validated in this same manner to prevent false framing. If there were any error(s), they are
reported in the LSR register bits [4:1]. Upon unloading the receive data byte from RHR, the receive FIFO
pointer is bumped and the error flags are immediately updated to reflect the status of the data byte in RHR
register. RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches
the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out
function when receive data does not reach the receive FIFO trigger level. This time-out delay is 4 word lengths
as defined by LCR bits [1:0] plus 12 bits time. The RHR interrupt is enabled by IER bit [0].
3.7.1
Receiver Operation in non-FIFO Mode
FIGURE 15. RECEIVER OPERATION IN NON-FIFO MODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
16X or 8X or 4X
Clock
Receive Data Characters
Data Bit
Validation
Error
Flags in
LSR bits
4:2
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XR17V358IB176-F 制造商:Exar Corporation 功能描述:IC OCTAL UART 25MBPS 3.6V 176-BGA
XR17V358IB-E4-EVB 功能描述:界面開(kāi)發(fā)工具 Eval Board for XR17V358IB-E4 RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V
XR17V358IB-E8-EVB 功能描述:界面開(kāi)發(fā)工具 Eval Board for XR17V358IB-E8 RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V
XR1857SN 制造商:Electro-Term/Hollingsworth 功能描述:
XR1858SN 制造商:Electro-Term/Hollingsworth 功能描述:
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