REV. 1.0.4 3.2 Automatic Hardware (RTS/CTS or DTR/DSR) Flow Control Operation" />
參數(shù)資料
型號: XR17V358IB176-F
廠商: Exar Corporation
文件頁數(shù): 32/68頁
文件大?。?/td> 0K
描述: IC UART PCIE OCTAL 176FPBGA
產品培訓模塊: PCIe UARTs
UART Product Overview
標準包裝: 160
特點: *
通道數(shù): 1,UART
FIFO's: 256 字節(jié)
規(guī)程: RS485
電源電壓: 1.2V,3.3V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調制解調器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 176-LFBGA
供應商設備封裝: 176-FPBGA(13x13)
包裝: 托盤
配用: 1016-1296-ND - EVAL BOARD FOR XR17V358-E8
1016-1295-ND - EVAL BOARD FOR XR17V358-E4
1016-1293-ND - EVAL BOARD FOR XR17V358
其它名稱: 1016-1294
XR17V358
38
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
REV. 1.0.4
3.2
Automatic Hardware (RTS/CTS or DTR/DSR) Flow Control Operation
Automatic hardware or RTS/DTR and CTS/DSR flow control is used to prevent data overrun to the local
receiver FIFO and remote receiver FIFO. The RTS#/DTR# output pin is used to request remote unit to
suspend/restart data transmission while the CTS#/DSR# input pin is monitored to suspend/restart local
transmitter. The auto RTS/DTR and auto CTS/DSR flow control features are individually selected to fit specific
application requirement and enabled through EFR bit[7:6] and MCR bit [2] for either RTS/CTS or DTR/DSR
control signals. The auto RTS/DTR function must be started by asserting RTS/DTR# output pin (MCR bit [0] or
bit [1] to logic 1) after it is enabled. Figure 10 below explains how it works.
Two interrupts associated with RTS/DTR and CTS/DSR flow control have been added to give indication when
RTS/DTR# pin or CTS/DSR# pin is de-asserted during operation. The RTS/DTR and CTS/DSR interrupts must
be first enabled by EFR bit [4], and then enabled individually by IER bits [7:6], and chosen with MCR bit [2].
Automatic hardware flow control is selected by setting bits [7 (CTS): 6 (RTS)] of the EFR register to logic 1. If
CTS# pin transitions from LOW to HIGH indicating a flow control request, ISR bit [5] will be set to logic 1, (if
enabled via IER bit [7:6]), and the UART will suspend TX transmissions as soon as the stop bit of the character
in process is shifted out. Transmission is resumed after the CTS# input returns to LOW, indicating more data
may be sent.
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