REV. 1.0.4 HIGH PERFORMANCE OCTAL PCI EXPRESS UART TABLE 14: UART CH" />
參數(shù)資料
型號(hào)： XR17V358IB-E8-EVB
廠商： Exar Corporation
文件頁(yè)數(shù)： 38/68頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR17V358-E8
產(chǎn)品培訓(xùn)模塊： PCIe UARTs
UART Product Overview
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，UART
嵌入式： 否
已用 IC / 零件： XR17V358
已供物品： 板
相關(guān)產(chǎn)品： 1016-1294-ND - IC UART PCIE OCTAL 176FPBGA
其它名稱： 1016-1296
XR17V358
43
REV. 1.0.4
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
TABLE 14: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4.
ADDRESS
A3-A0
REG
NAME
READ/
WRITE
BIT [7]
BIT [6]
BIT [5]
BIT [4]
BIT [3]
BIT [2]
BIT[1]
BIT [0]
COMMENT
0 0 0 0
RHR
R
BIT [7]
BIT [6]
Bit [5]
Bit [4]
Bit [3]
Bit [2]
Bit [1]
Bit [0]
LCR[7]=0
0 0 0 0
THR
W
BIT [7]
BIT [6]
Bit [5]
Bit [4]
Bit [3]
Bit [2]
Bit [1]
Bit [0]
LCR[7]=0
0 0 0 0
DLL
R/W
BIT [7]
BIT [6]
Bit [5]
Bit [4]
Bit [3]
Bit [2]
Bit [1]
Bit [0]
LCR[7]=1
0 0 0 1
DLM
R/W
BIT [7]
BIT [6]
Bit [5]
Bit [4]
Bit [3]
Bit [2]
Bit [1]
Bit [0]
LCR[7]=1
0 0 1 0
DLD
R/W
Invert
RS485
Polarity
Multi-
drop
mode
XON/
XOFF
parity
check
Fast IR
mode
Bit [3]
Bit [2]
Bit [1]
Bit [0]
LCR[7]=1
0 0 0 1
IER
R/W
0/
0
Modem
Status
Int.
Enable
RX Line
Status
Int.
Enable
TX
Empty
Int.
Enable
RX Data
Int.
Enable
LCR[7]=0
CTS/
DSR#
Int.
Enable
RTS/
DTR#
Int.
Enable
Xon/
Xoff/Sp.
Char. Int.
Enable
0 0 1 0
ISR
R
FIFOs
Enable
FIFOs
Enable
0/
INT
Source
Bit [3]
INT
Source
Bit [2]
INT
Source
Bit [1]
INT
Source
Bit [0]
LCR[7]=0
Delta-
Flow
Cntl
Xoff/spe-
cial char
0 0 1 0
FCR
W
RXFIFO
Trigger
RXFIFO
Trigger
0/
DMA
Mode
TX FIFO
Reset
RX FIFO
Reset
FIFOs
Enable
LCR[7]=0
TXFIFO
Trigger
TX FIFO
Trigger
0 0 1 1
LCR
R/W
Divisor
Enable
Set TX
Break
Set Par-
ity
Even Par-
ity
Parity
Enable
Stop Bits
Word
Length
Bit [1]
Word
Length
Bit [0]
0 1 0 0
MCR
R/W
0/
Internal
Loopback
Enable
(OP2)1
(OP1)1
RTS#
Pin Con-
trol
DTR#
Pin Con-
trol
BRG
Pres-
caler
IR
Enable
XonAny
TX char
Immedi-
ate
RTS/
DTR
Flow Sel
0 1 0 1
LSR
R
RX FIFO
Error
TSR
Empty
THR
Empty
RX Break
RX
Framing
Error
RX Par-
ity Error
RX
Overrun
RX Data
Ready
0 1 1 0
MSR
R
CD
RI
DSR
CTS
Delta
CD#
Delta
RI#
Delta
DSR#
Delta
CTS#
MSR
W
RS485
DLY[3]
RS485
DLY[2]
RS485
DLY[1]
RS485
DLY[0]
Disable
TX
Disable
RX
Disable
TX mode
Disable
RX mode
0 1 1 1
SPR
R/W
Bit [7]
Bit [6]
Bit [5]
Bit [4]
Bit [3]
Bit [2]
Bit [1]
Bit [0]
User Data
1 0 0 0
FCTR
R/W
TRG
Table
Bit [1]
TRG
Table
Bit [0]
Auto
RS485
Enable
Invert IR
RX Input
RTS/
DTR
Hyst
Bit [3]
RTS/
DTR
Hyst
Bit [2]
RTS/
DTR
Hyst
Bit [1]
RTS/
DTR
Hyst
Bit [0]
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