REV. 1.0.4 Each bit gives an indication of the channel that has requested for service. Bit " />
參數(shù)資料
型號(hào)： XR17V358IB-E8-EVB
廠商： Exar Corporation
文件頁(yè)數(shù)： 13/68頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR17V358-E8
產(chǎn)品培訓(xùn)模塊： PCIe UARTs
UART Product Overview
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，UART
嵌入式： 否
已用 IC / 零件： XR17V358
已供物品： 板
相關(guān)產(chǎn)品： 1016-1294-ND - IC UART PCIE OCTAL 176FPBGA
其它名稱： 1016-1296
XR17V358
20
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
REV. 1.0.4
Each bit gives an indication of the channel that has requested for service. Bit [0] represents channel 0 and
bit [7] indicates channel 7. Logic 1 indicates the channel N [7:0] has called for service. The interrupt bit clears
after reading the appropriate register of the interrupting channel register, see Interrupt Clearing section.
The INT0 register provides individual status for each channel
INT0 Register
Individual UART Channel Interrupt Status
Ch-6
Ch-7
Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
INT3, INT2 and INT1 [31:8] 3-bit Channel Interrupt Encoding
Each channel’s interrupt is encoded into 3 bits for receive, transmit, and status. Bits [10:8] represent channel 0
and go up to channel 7 with bits [31:29]. The 3-bit encoding and their priority order are shown below in Table 7.
The wake-up interrupt, timer/counter interrupt and MPIO interrupt are only reported in channel 0 of INT1
(bits[10:8]). These interrupts are not reported in any other location.
FIGURE 4. THE GLOBAL INTERRUPT REGISTER, INT0, INT1, INT2 AND INT3
Channel-3
Channel-2
Channel-1
Channel-0
INT2 Register
INT1 Register
INT3 Register
INT0 Register
Interrupt Registers,
INT0, INT1, INT2 and INT3
Bit-0
Bit-1
Bit-2
Bit-3
Bit-7
Bit-4
Bit-5
Bit-6
Ch-3 Ch-2 Ch-1 Ch-0
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Ch-7 Ch-6 Ch-5 Ch-4
Channel-7
Channel-6
Channel-5
Channel-4
TABLE 7: UART CHANNEL [7:0] INTERRUPT SOURCE ENCODING
PRIORITY
BIT[N+2]
BIT[N+1]
BIT[N]
INTERRUPT SOURCE(S)
x
0
None or wake-up indicator (wake-up indicator is reported in channel 0 only)
1
0
1
RXRDY and RX Line Status (logic OR of LSR[4:1])
2
0
1
0
RXRDY Time-out
3
0
1
TXRDY, THR or TSR (auto RS485 mode) empty
4
1
0
MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon det. or special char. detected
5
1
0
1
Reserved.
6
1
0
MPIO pin(s). Reported in channel 0 only.
7
1
Timer/Counter. Reported in channel 0 only.
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