REV. 1.0.4 FCR[3]: DMA Mode Select This bit has no effect since TXRDY and RXRDY pins are no" />
參數(shù)資料
型號(hào)： XR17V358IB-E4-EVB
廠商： Exar Corporation
文件頁(yè)數(shù)： 48/68頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR17V358-E4
產(chǎn)品培訓(xùn)模塊： PCIe UARTs
UART Product Overview
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，UART
嵌入式： 否
已用 IC / 零件： XR17V358
已供物品： 板
相關(guān)產(chǎn)品： 1016-1294-ND - IC UART PCIE OCTAL 176FPBGA
其它名稱(chēng)： 1016-1295
XR17V358
52
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
REV. 1.0.4
FCR[3]: DMA Mode Select
This bit has no effect since TXRDY and RXRDY pins are not available in this device. It is provided for legacy
software compatibility.
Logic 0 = Set DMA to mode 0 (default).
Logic 1 = Set DMA to mode 1.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit [0] is active.
Logic 0= No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit [0] is active.
Logic 0 = No receive FIFO reset (default).
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[0]: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
TABLE 16: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION
TRIGGER
TABLE
FCTR
BIT [7]
FCTR
BIT [6]
FCR
BIT [7]
FCR
BIT [6]
FCR
BIT [5]
FCR
BIT [4]
RECEIVE
TRIGGER LEVEL
TRANSMIT
TRIGGER
LEVEL
COMPATIBILITY
Table-A
0
1
0
1
0
1
0
1 (default)
4
8
14
1 (default)
16C550, 16C2550,
16C2552, 16C554,
16C580, 16L580
Table-B
0
1
0
1
0
1
0
1
0
1
0
1
0
1
8
16
24
28
16
8
24
30
16C650A, 16L651
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