REV. 1.0.4 HIGH PERFORMANCE OCTAL PCI EXPRESS UART 2.0 TRANSMIT AND RECEIVE DATA There are two methods to load transmit data and un" />
參數(shù)資料
型號(hào)： XR17V358IB-E4-EVB
廠商： Exar Corporation
文件頁(yè)數(shù)： 25/68頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR17V358-E4
產(chǎn)品培訓(xùn)模塊： PCIe UARTs
UART Product Overview
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，UART
嵌入式： 否
已用 IC / 零件： XR17V358
已供物品： 板
相關(guān)產(chǎn)品： 1016-1294-ND - IC UART PCIE OCTAL 176FPBGA
其它名稱： 1016-1295
XR17V358
31
REV. 1.0.4
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
2.0 TRANSMIT AND RECEIVE DATA
There are two methods to load transmit data and unload receive data from each UART channel. First, there is
a transmit data register and receive data register for each UART channel as shown in Table 4 set to ease
programming. These registers support 8, 16, 24 and 32 bits wide format. In the 32-bit format, it increases the
data transfer rate on the PCI bus. Additionally, a special register location provides receive data byte with its
associated error flags. This is a 16-bit or 32-bit read operation where the Line Status Register (LSR) content in
the UART channel register is paired along with the data byte. This operation further facilitates data unloading
with the error flags without having to read the LSR register separately. Furthermore, the XR17V358 supports
32-bit read/write operation.
The second method is through each UART channel’s transmit holding register (THR) and receive holding
register (RHR). The THR and RHR registers are 16550 compatible so their access is limited to 8-bit format.
The software driver must separately read the LSR content for the associated error flags before reading the
data byte.
2.1
FIFO DATA LOADING AND UNLOADING IN 32-BIT FORMAT
The XR17V358 supports 32-bit Read and 32-bit Write transactions anywhere in the mapped memory region
(except reserved areas). In addition, to utilize this feature fully, the device provides a separate memory location
(apart from the individual channel’s register set) where the RX and the TX FIFO can be read from/written to, as
shown in Table 4. The following is an extract from the table showing the memory locations that support 32-bit
transactions:
Channel N: (for channels 0 through 7) where M = 4N + 1.
RX FIFO
:
0xM00 - 0xMFF (256 bytes)
TX FIFO
:
0xM00 - 0xMFF (256 bytes)
RX FIFO + status
:
0x(M+1)0 - 0x(M+2)FF (256 bytes data + 256 bytes status)
For example, the locations for channel 2 are:
Channel 2:
RX FIFO
:
0x0900 - 0x09FF (256 bytes)
TX FIFO
:
0x0900 - 0x09FF (256 bytes)
RX FIFO + status
:
0x0A00 - 0x0BFF (256 bytes data + 256 bytes status)
2.1.1
Normal Rx FIFO Data Unloading at locations 0x100, 0x500, 0x900, 0xD00, 0x1100, 0x1500,
0x1900, and 0x1D00
The RX FIFO data can be read out 32-bits at a time at memory locations 0x100 (channel 0), 0x500 (channel 1),
0x900
(channel 2),......., 0x1D00 (channel 7). This operation is 4 times faster than reading the data in 256
separate 8-bit memory reads of RHR register (0x000 for channel 0, 0x400 for channel 1, 0x800 for channel
2,......, 0x1C00 for channel 7).
READ RX FIFO,
WITH NO ERRORS
BYTE 3
BYTE 2
BYTE 1
BYTE 0
Read n+0 to n+3
FIFO Data n+3
FIFO Data n+2
FIFO Data n+1
FIFO Data n+0
Read n+4 to n+7
FIFO Data n+7
FIFO Data n+6
FIFO Data n+5
FIFO Data n+4
Etc.
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