參數(shù)資料
型號(hào): XR17V354IB176-F
廠商: Exar Corporation
文件頁數(shù): 13/66頁
文件大?。?/td> 0K
描述: IC UART PCIE 256B QUAD 176FPBGA
產(chǎn)品培訓(xùn)模塊: PCIe UARTs
標(biāo)準(zhǔn)包裝: 160
特點(diǎn): *
通道數(shù): 4,QUART
FIFO's: 256 字節(jié)
規(guī)程: RS485
電源電壓: 3.3V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 176-LFBGA
供應(yīng)商設(shè)備封裝: 176-FPBGA(13x13)
包裝: 托盤
其它名稱: 1016-1472
XR17V354IB176-F-ND
TIM E RM SB Register
B it-1 5
B it-1 4
B it-1 3
B it-1 2
B it-1 1
B it-1 0
B it-9
B it-8
TIM ERLSB Register
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1 B it-0
16-B it T im er/C ou nte r P rog ra m m ab le R e gisters
XR17V354
20
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
REV. 1.0.3
REGA [15:8] Register
Reserved.
TIMERCNTL [7:0] Register
The bits [3:0] of this register are used to issue commands. The commands are self-clearing, so reading this
register does not show the last written command. Reading this register returns a value of 0x01 when the Timer
interrupt is enabled and there is a pending Timer interrupt. It returns a value of 0x00 at all other times. The
default settings of the Timer, upon power-up, a hardware reset or upon the issue of a ’Timer Reset’ command
are:
Timer Interrupt Disabled
Re-triggerable mode selected
Internal 125MHz clock (master) or 62.5MHz clock (slave) selected as clock source
Timer output not routed to MPIO[0]
Timer stopped
TABLE 9: TIMER CONTROL REGISTERS
TIMERCNTL [7:4] Reserved
TIMERCNTL [3:0] These bits are used to invoke a series of commands that control the function of the Timer/Counter.
The commands 1100 to 1111 are reserved.
0001: Enable Timer Interrupt
0010: Disable Timer Interrupt
0011: Select One-shot mode
0100: Select Re-triggerable mode
0101: Select Internal 125MHz clock (master) or 62.5MHz clock (slave) as clock input for the Timer
0110: Select External Clock input through the TMRCK pin for the Timer
0111: Route Timer output to MPIO[0] pin
1000: De-route Timer output from MPIO[0]
1001: Start Timer
1010: Stop Timer
1011: Reset Timer
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