
XR17V252
61
REV. 1.0.2
66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT
FIGURE 21. DEVICE CONFIGURATION REGISTERS, UART REGISTERS AND TRANSMIT DATA BURST WRITE OPERA-
TION
CLK
FRAME#
AD[31:0]
C/BE[3:0]#
TRDY#
IRDY#
DEVSEL#
1
23
4
Address
Bus
CMD
Byte Enable# = DWORD
PCI BWR
5
6
7
PAR
PERR#
8
Note: PERR# and SERR are optional in a bus target application.
Even Parity is on AD[31:0], C/BE[3:0]#, and PAR
Host
Target
Host
Target
Address
Parity
SERR#
Target
Active
Data
Parity
Active
910
Data
DWORD
Data DWORD
DWO
R
D
T
R
ANSFER
DWO
R
D
T
R
ANSFER
DWO
R
D
T
R
ANSFER
DWO
R
D
T
R
ANSFER
DWO
R
D
T
R
ANSFER
Data
Parity
Data
Parity
Data
Parity
Data
Parity
Active
11
Data
DWORD
Data
DWORD
Data
DWORD