參數(shù)資料
型號(hào): XR17D152IM
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
中文描述: 2 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP100
封裝: 14 X 14 MM, 1 MM HEIGHT, TQFP-100
文件頁(yè)數(shù): 45/68頁(yè)
文件大?。?/td> 772K
代理商: XR17D152IM
á
REV. 1.2.0
XR17D152
UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
45
MSR[5]: DSR Input Status
This input may be used for auto DTR/DSR flow control function, see
“Section 5.4, Automatic Hardware (RTS/
CTS or DTR/DSR) Flow Control Operation” on page 30
for complete details. If automatic hardware flow control
is not used, this bit is the compliment of the DSR# input. In the loopback mode, this bit is equivalent to the
DTR# bit in the MCR register. The DSR# input may be used as a general purpose input when the modem
interface is not used.
MSR[6]: RI Input Status
This bit is the compliment of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the MCR
register. The RI# input may be used as a general purpose input when the modem interface is not used.
MSR[7]: CD Input Status
This bit is the compliment of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the MCR
register. The CD# input may be used as a general purpose input
5.8.11
Modem Status Register (MSR) - Write-Only
The upper four bits 4-7 of this register sets the delay in number of bits time for the auto RS485 turn around from
transmit to receive.
MSR [7:4]
When Auto RS485 feature is enabled (FCTR bit-5=1) and RTS# output is connected to the enable input of a
RS-485 transceiver. These 4 bits select from 0 to 15 bit-time delay after the end of the last stop-bit of the last
transmitted character. This delay controls when to change the state of RTS# output. This delay is very useful in
long-cable networks.
Table 16
shows the selection. The bits are enabled by EFR bit-4.
T
ABLE
16: A
UTO
RS485 H
ALF
-
DUPLEX
D
IRECTION
C
ONTROL
D
ELAY
FROM
T
RANSMIT
-
TO
-R
ECEIVE
MSR[7]
MSR[6]
MSR[5]
MSR[4]
D
ELAY
IN
D
ATA
B
IT
(
S
) T
IME
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
9
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
1
0
1
0
10
1
0
1
1
11
1
1
0
0
12
1
1
0
1
13
1
1
1
0
14
1
1
1
1
15
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