參數(shù)資料
型號: XR17D152CM-0A-EVB
廠商: Exar Corporation
文件頁數(shù): 9/68頁
文件大小: 0K
描述: EVAL BOARD FOR XR17D152 100TQFP
標準包裝: 1
系列: *
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XR17D152
REV. 1.2.0
UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
17
TIMERMSB [31:24] and TIMERLSB [23:16]
TIMERMSB and TIMERLSB form a 16-bit value. The least-significant bit of the timer is being bit [0] of the
TIMERLSB with most-significant-bit being bit-7 in TIMERMSB. Notice that these registers do not hold the
current counter value when read. Reading the TIMERCNTL register will clear its interrupt. Default value is zero
(timer disabled) upon powerup and reset.
2.2.3
8XMODE [7:0] (default 0x00)
Each bit selects 8X or 16X sampling rate for that UART channel, bit-0 is channel 0. Logic 0 (default) selects
normal 16X sampling with logic one selects 8X sampling rate. Transmit and receive data rates will double by
selecting 8X.
2.2.4
REGA [15:8] Reserved
2.2.5
RESET [23:16] - (default 0x00)
Bits 0 to 1 of the Reset register [RESET] provides the software with the ability to reset the UART(s) when there
is a need. Each bit is self-resetting after it is written a logic 1 to perform a reset to that channel. All registers in
that channel will be reset to the default condition, see Table 19 on page 50 for details. Bit-0 =1 resets UART
channel 0 while bit-1=1 resets channel 1.
TIM E RM SB Reg ister
B it-1 5
B it-1 4
B it-1 3
B it-1 2
B it-1 1
B it-1 0
B it-9
B it-8
TIM E RLS B Register
B it-7
B it-6
B it-5
B it-4
B it-3
B it-2
B it-1 B it-0
16-B it T im e r/C o u n te r P rog ra m m able R e gisters
Rsvd
Rsvd Rsvd Rsvd Rsvd Ch-1 Ch-0
8XM O DE Register
Individual UA RT Channel 8X Clock Mode E nable
B it-7 Bit-6
B it-5
B it-4
Bit-3
Bit-2
B it-1 B it-0
Rsvd
Rsvd Rsvd Rsvd Rsvd Ch-1 Ch-0
RES ET Register
Individual UA RT Channel Reset Enable
B it-7 Bit-6
B it-5
B it-4
Bit-3
B it-2
B it-1
Bit-0
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