- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16514 > XR17D152CM-0A-EVB (Exar Corporation)EVAL BOARD FOR XR17D152 100TQFP PDF資料下載
參數(shù)資料
| 型號： | XR17D152CM-0A-EVB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 20/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR XR17D152 100TQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
á
XR17D152
REV. 1.2.0
UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
27
5.2
Transmitter
The transmitter section comprises of 64 bytes of FIFO, a byte-wide Transmit Holding Register (THR) and an 8-
bit Transmit Shift Register (TSR). THR receives a data byte from the host (non-FIFO mode) or a data byte from
the FIFO when the FIFO is enabled by FCR bit-0. TSR shifts out every data bit with the 16X or 8X internal
clock. A bit time is 16 or 8 clock periods. The transmitter sends the start bit followed by the number of data bits,
inserts the proper parity bit if enable, and adds the stop bit(s). The status of the THR and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
5.2.1
Transmit Holding Register (THR) - Write-Only
The Transmit Holding Register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is also the
input register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. A THR empty
interrupt can be generated when it is enabled in IER bit-1.
5.2.2
Transmitter Operation in non-FIFO mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
5.2.3
Transmitter Operation in FIFO mode
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level (see TXTRG register). The transmit empty
interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
Furthermore, with the RS485 half-duplex direction control enabled (FCTR bit-5=1) the source of the transmit
empty interrupt changes to TSR empty instead of THR empty. This is to ensure the RTS# output is not
changed until the last stop bit of the last character is shifted out.
5.2.4
Auto RS485 Operation
The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled during
powerup or reset by the EN485# pin or in software by FCTR bit-5. While transmitting, the RTS# or DTR# signal
is HIGH. The RTS# or DTR# signal changes from a HIGH to a LOW after a specified delay indicated in
MSR[7:4] following the last stop bit of the last character that has been transmitted. This helps in turning around
the transceiver to receive the remote station’s response. The delay optimizes the time needed for the last
transmission to reach the farthest station on a long cable network before switching off the line driver. This delay
prevents undesirable line signal disturbance that causes signal degradation. It also changes the transmitter
empty interrupt to TSR empty instead of THR empty.
FIGURE 12. TRANSMITTER OPERATION IN NON-FIFO MODE
T rans m it
H o ld in g
R e g ister
(T HR)
T rans m it Shift R egis ter (T S R )
Da ta
By te
L
S
B
M
S
B
T H R In te r ru p t (IS R b it-1 )
E nabled by IE R bit-1
TXN O FIFO 1
16X or 8X
Clo c k
(8 X M O D E
R e g ister )
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CB2012T100MR | INDUCTOR POWER 10UH 0805 |
| RBC26DRXH | CONN EDGECARD 52POS DIP .100 SLD |
| 6374612-4 | C/A 50/125 MM SC-LC 4M |
| GBM36DCSH-S288 | CONN EDGECARD 72POS .156 EXTEND |
| EMC06DRAS | CONN EDGECARD 12POS R/A .100 SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR17D152CM-F | 功能描述:UART 接口集成電路 3.3V-5V 64B FIFO temp 0C to 70C; UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR17D152CMTR-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR17D152IM | 制造商:EXAR 制造商全稱:EXAR 功能描述:UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART |
| XR17D152IM-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR17D154 | 制造商:EXAR 制造商全稱:EXAR 功能描述:UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。