REV. 1.0.3 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO 2.9.1 Transmit Holding Register (THR) - Write Only The transmit holding r" />
參數(shù)資料
型號(hào)： XR16V554DIV-0A-EB
廠商： Exar Corporation
文件頁(yè)數(shù)： 7/43頁(yè)
文件大小： 0K
描述： EVAL BOARD FOR XR16V554D 64LQFP
標(biāo)準(zhǔn)包裝： 1
系列： *
XR16V554/554D
15
REV. 1.0.3
2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO
2.9.1
Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.9.2
Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE
Transmit
Holding
Register
(THR)
Transmit Shift Register (TSR)
Data
Byte
L
S
B
M
S
B
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
TXNOFIFO1
16X Clock
2.9.3
Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set
when TSR/FIFO becomes empty.
FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit Data Shift Register
( TSR)
Transmit
Data Byte
THR Interrupt (ISR bit-1)
When it becomes empty.
FIFO is Enabled by FCR
Bit-0=1
Transmit
FIFO
16X Clock
TXFIFO1
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