REV. 1.0.2 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE 2.13 Auto RTS Hysteresis The V2651 has a n" />
參數(shù)資料
型號: XR16V2651IM-0B-EB
廠商: Exar Corporation
文件頁數(shù): 9/51頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR V2651 48TQFP
標準包裝: 1
系列: *
XR16V2651
17
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
2.13
Auto RTS Hysteresis
The V2651 has a new feature that provides flow control trigger hysteresis while maintaining compatibility with
the XR16C850, ST16C650A and ST16C550 family of UARTs. With the Auto RTS function enabled, an interrupt
is generated when the receive FIFO reaches the selected RX trigger level. The RTS# pin will not be forced
HIGH (RTS off) until the receive FIFO reaches one level above the selected RX trigger level in the trigger table
(Table 12). The RTS# pin will return LOW after the RX FIFO is unloaded to one level below the selected RX
trigger level in the trigger table (Table 12). Under the above described conditions, the V2651 will continue to
accept data until the receive FIFO gets full. The Auto RTS function is initiated when the RTS# output pin is
asserted LOW (RTS On).
2.14
Auto CTS Flow Control
Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is
monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific
application requirement (see Figure 10):
Enable auto CTS flow control using EFR bit-7.
If using the Auto CTS interrupt:
Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the
CTS# pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend transmission as soon as
the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re-
asserted (LOW), indicating more data may be sent.
TABLE 7: AUTO RTS (HARDWARE) FLOW CONTROL
RX TRIGGER LEVEL
INT PIN ACTIVATION
RTS# DE-ASSERTED (HIGH)
(CHARACTERS IN RX FIFO)
RTS# ASSERTED (LOW)
(CHARACTERS IN RX FIFO)
8
16
0
16
24
8
24
28
16
28
24
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