REV. 1.0.2 EFR[6]: Auto RTS Flow Control Enable RTS# output may be used for hardware flow" />
參數(shù)資料
型號: XR16V2650IL-0B-EB
廠商: Exar Corporation
文件頁數(shù): 28/47頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR V2650 32QFN
標準包裝: 1
系列: *
XR16V2650
34
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
REV. 1.0.2
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the selected trigger level and RTS de-
asserts HIGH at the next upper trigger level. RTS# will return LOW when FIFO data falls below the next lower
trigger level. The RTS# output must be asserted (LOW) before the auto RTS can take effect. RTS# pin will
function as a general purpose output when hardware flow control is disabled.
Logic 0 = Automatic RTS flow control is disabled (default).
Logic 1 = Enable Automatic RTS flow control.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
Logic 0 = Automatic CTS flow control is disabled (default).
Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts HIGH.
Data transmission resumes when CTS# returns LOW.
4.14.1
Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, see Table 7.
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