REV. 1.0.3 2.20 Internal Loopback The V2550 UART provides an internal loopb" />
參數(shù)資料
型號(hào)： XR16V2550IM-0B-EB
廠商： Exar Corporation
文件頁(yè)數(shù)： 13/46頁(yè)
文件大小： 0K
描述： EVAL BOARD FOR V2550 48TQFP
標(biāo)準(zhǔn)包裝： 1
系列： *
XR16V2550
20
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
REV. 1.0.3
2.20
Internal Loopback
The V2550 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 12 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX, RTS# and DTR# pins are held while the CTS#, DSR#, CD# and RI# inputs are ignored.
Caution: the RX input pin must be held HIGH during loopback test,+ else upon exiting the loopback test the
UART may detect and report a false “break” signal. Also, auto RTS/CTS flow control is not supported during
internal loopback.
FIGURE 12. INTERNAL LOOP BACK IN CHANNEL A AND B
TXA/TXB
RXA/RXB
Modem
/Ge
n
er
al
Pur
p
os
e
Co
nt
rol
Logic
In
tern
al
Da
ta
Bu
s
Lines
a
nd
Co
n
tro
lSign
a
ls
RTSA#/RTSB#
MCR bit-4=1
VCC
Transmit Shift Register
(THR/FIFO)
Receive Shift Register
(RHR/FIFO)
CTSA#/CTSB#
DTRA#/DTRB#
DSRA#/DSRB#
RIA#/RIB#
CDA#/CDB#
OP1#
OP2#
RTS#
CTS#
DTR#
DSR#
RI#
CD#
VCC
OP2A#/OP2B#
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