參數(shù)資料
型號(hào): XR16L2550IM
廠商: EXAR CORP
元件分類(lèi): 微控制器/微處理器
英文描述: LOW VOLTAGE DUART WITH 16-BYTE FIFO
中文描述: 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQFP48
封裝: 7 X 7 MM, 1 MM HEIGHT, TQFP-48
文件頁(yè)數(shù): 27/45頁(yè)
文件大小: 278K
代理商: XR16L2550IM
á
REV. 1.0.0
XR16L2550
LOW VOLTAGE DUART WITH 16-BYTE FIFO
27
3.6
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
Line Control Register (LCR) - Read/Write
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See
Table 11
for parity selection summary below.
Logic 0 = No parity.
Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
T
ABLE
10: R
ECEIVE
FIFO T
RIGGER
L
EVEL
S
ELECTION
FCR B
IT
-7
FCR B
IT
-6
R
ECEIVE
T
RIGGER
L
EVEL
C
OMPATIBILITY
0
0
1
1
0
1
0
1
1 (default)
4
8
14
16C550, 16C2550,
16C2552, 16C554,
16C580 compatible.
BIT-1
BIT-0
W
ORD
LENGTH
0
0
5 (default)
0
1
6
1
0
7
1
1
8
BIT-2
W
ORD
LENGTH
S
TOP
BIT
LENGTH
(B
IT
TIME
(
S
))
0
5,6,7,8
1 (default)
1
5
1-1/2
1
6,7,8
2
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