參數(shù)資料
型號(hào)： XR16L2550IM
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： LOW VOLTAGE DUART WITH 16-BYTE FIFO
中文描述： 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQFP48
封裝： 7 X 7 MM, 1 MM HEIGHT, TQFP-48
文件頁(yè)數(shù)： 26/45頁(yè)
文件大?。?/td> 278K
代理商： XR16L2550IM
XR16L2550
LOW VOLTAGE DUART WITH 16-BYTE FIFO
á
REV. 1.0.0
26
ISR[4]: Xoff or Special Character Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match
of the Xoff character(s). If this is an Xoff interrupt, it can be cleared by a read to the ISR or when an Xon
character is received. If it is a special character interrupt, it will automatically clear after the next character is
received.
ISR[5]: RTS#/CTS# Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-5 indicates that the CTS# or RTS# has changed
state from low to high.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
3.5
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No receive
FIFO
reset (default)
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of theTXRDY# and RXRDY# pins. See DMA operation section for details.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
FCR[5:4]: Reserved
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level.
Table 10
shows the complete selections.
相關(guān)PDF資料
PDF描述
XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO
XR16L2551 LOW VOLTAGE DUART WITH POWERSAVE
XR16L2551IL LOW VOLTAGE DUART WITH POWERSAVE
XR16L2551IM LOW VOLTAGE DUART WITH POWERSAVE
XR16L2552IJ 2.25V TO 5.5V DUART WITH 16-BYTE FIFO
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XR16L2550IM-0A-EB 功能描述:界面開發(fā)工具 Supports L2550 48 ld TQFP, ISA Interface RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
XR16L2550IM-0B-EB 功能描述:UART 接口集成電路 Supports L2550 48 ld TQFP, PCI Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16L2550IM-F 功能描述:UART 接口集成電路 2.5V-5.5V 16B FIFO temp -45 to 85C;UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16L2550IMTR-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16L2551 制造商:EXAR 制造商全稱:EXAR 功能描述:LOW VOLTAGE DUART WITH POWERSAVE
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