REV. 2.1.1 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS 7 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data" />
參數(shù)資料
型號： XR16C2852IJ-F
廠商： Exar Corporation
文件頁數(shù)： 49/51頁
文件大小： 0K
描述： IC UART FIFO 128B 44PLCC
標準包裝： 27
特點： *
通道數(shù)： 2，DUART
FIFO's： 128 字節(jié)
規(guī)程： RS232，RS485
電源電壓： 2.97 V ~ 5.5 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應商設(shè)備封裝： 44-PLCC（16.59x16.59）
包裝： 管件
其它名稱： 1016-1659
XR16C2852IJ-F-ND
xr
XR16C2852
REV. 2.1.1
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
7
2.0 FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The 2852 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CHSEL, CS#, IOR# and IOW# signals. Both UART
channels share the same data bus for host operations. The data bus interconnections are shown in Figure 3.
.
2.2
Device Reset
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see Table 16 on page 38). An active high pulse of longer than 40 ns duration will be required to activate
the reset function in the device.
2.3
Device Identification and Revision
The XR16C2852 provides a Device Identification code and a Device Revision code to distinguish the part from
other devices and revisions. To read the identification code from the part, it is required to set the baud rate
generator registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x12 for the
XR16C2852 and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01
means revision A.
2.4
Channel A and B Selection
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. A logic 0 on chip select pin (CS#) allows the user to select
the UART and then using the channel select (CHSEL) pin, the user can select channel A or B to configure,
send transmit data and/or unload receive data to/from the UART. Individual channel select functions are shown
FIGURE 3.
XR16C2852 DATA BUS INTERCONNECTIONS
VCC
(OP2A#)
DSRA#
CTSA#
RTSA#
DTRA#
RXA
TXA
RIA#
CDA#
(OP2B#)
DSRB#
CTSB#
RTSB#
DTRB#
RXB
TXB
RIB#
CDB#
GND
A0
A1
A2
UART_CS#
UART_CHSEL
IOR#
IOW#
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
CS#
CHSEL
D0
D1
D2
D3
D4
D5
D6
D7
IOR#
IOW#
UART
Channel A
UART
Channel B
UART_INTB
UART_INTA
INTB
INTA
(RXRDYA#)
TXRDYA#
(RXRDYA#)
TXRDYA#
(RXRDYB#)
TXRDYB#
(RXRDYB#)
TXRDYB#
UART_RESET
RESET
Serial Interface of
RS-232, RS-485
Serial Interface of
RS-232, RS-485
2750int
(BAUDOUTB#)
(BAUDOUTA#)
Pins in parentheses become available through the MF# pin. MF# A/B becomes RXRDY# A/B when AFR[2:1] = '10'. MF# A/B becomes OP2# A/B
when AFR[2:1] = '00'. MF# A/B becomes BAUDOUT# A/B when AFR[1:0] = '01'.
相關(guān)PDF資料
PDF描述
XR16C850IMTR-F IC UART FIFO 128B 48TQFP
XR16C854IQ-F IC UART FIFO 128B QUAD 100QFP
XR16C864IQ-F IC UART FIFO 128B QUAD 100QFP
XR16L2450IJ-F IC UART FIFO 1B DUAL 44PLCC
XR16L2550IJ-F IC UART FIFO 16B DUAL 44PLCC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XR16C2852IJTR-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR-16C450CJ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART
XR-16C450CP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART
XR-16C452CJ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART
XR-16C550CJ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*