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Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
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XR16C850
2.97V TO 5.5V UART WITH 128-BYTE FIFO
AUGUST 2005
REV. 2.3.1
GENERAL DESCRIPTION
The XR16C8501 (850) is a Universal Asynchronous
Receiver and Transmitter (UART). This device
supports Intel and PC mode data bus interface and is
software compatible to industry standard 16C450,
16C550, ST16C580 and ST16C650A UARTs.
The 850 has 128 bytes of TX and RX FIFOs and is
capable of operating up to a serial data rate of 2
Mbps. The internal registers include the 16C550
register set plus Exar’s enhanced registers for
additional
features
to
support
today’s
highly
demanding
data
communication
needs.
The
enhanced features include automatic hardware and
software flow control, selectable TX and RX trigger
levels, and wireless infrared (IrDA) encoder/decoder.
The XR16C850 is available in the 44 pin PLCC and
48 pin TQFP packages. They both provide the
standard Intel Bus mode and PC ISA bus (PC) mode.
The Intel Bus mode is compatible with the ST16C450
and ST16C550 while the PC mode allows connection
to the PC ISA bus.
NOTE: 1 Covered by U.S. patent #5,649,122 and #5,949,787.
FEATURES
Added feature in devices with top mark date code of
"F2 YYWW" and newer:
■ 5 volt tolerant inputs
■ 0 ns address hold time (TAH)
2.97 to 5.5 volt operation
Pin to pin compatible to ST16C550, ST16C580,
ST16C650A and TL16C750
128-byte Transmit and Receive FIFOs
Transmit/Receive FIFO Counters
Programmable TX/RX FIFO Trigger Levels
Automatic Hardware/Software Flow Control
Auto RS-485 half duplex direction support
Programmable Xon/Xoff characters
Infrared (IrDA) TX and RX Encoder/Decoder
Sleep Mode (100 uA stand-by)
APPLICATIONS
Battery Operated Electronics
Internet Appliances
Handheld Terminal
Personal Digital Assistants
Cellular Phones DataPort
Wireless Infrared Data Communications Systems
FIGURE 1. BLOCK DIAGRAM
X T AL 1/CL K
XT A L 2
C rystal O sc/B u ffer
DTR#, RT S#
DSR#, C T S #,
CD #, RI#
In tel o r
PC D ata
Bus
In terface
128 B yte T X F IF O
Baud Rate G enerato r
In frared
E n coder
T ran sm itter
UAR T
Configuratio n
Regs
IO R
IO R #
128 B yte R X F IF O
In frared
Decoder
R eceiver
M odem C ontro l S ignals
TX
RX
CTS Flow
Contro l
RTS Flow
Contro l
BR G
P rescaler
CS1
CS0
DD IS#
IN T
TX RD Y #
RX R D Y #
A2:A 0
D7:D 0
IO W
CS2#
PC M O D E #
S1
S2
S3
IR Q A
IR Q B
IR Q C
IO W #
R ESET
PC
M ode:
CO M 1 to
4
D ecode Logic