參數(shù)資料
型號： XR16C2852CJ
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： 3.3V AND 5V DUART WITH 128-BYTE FIFO
中文描述： 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 26/42頁
文件大?。?/td> 574K
代理商： XR16C2852CJ
á
3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2852
REV. 2.0.0
26
MCR[2]: Reserved
OP1# is not available as an output pin on the 2852.
But it is available for use during Internal Loopback
Mode. In the Loopback Mode, this bit is used to write
the state of the modem RI# interface signal.
MCR[3]: OP2# Output / INT Output Enable
OP2# is available as an output pin on the 2852 when
AFR[2:1] = ‘00’. In the Loopback Mode, MCR[3] is
used to write the state of the modem CD# interface
signal. Also see pin descriptions for MF# pins.
Logic 0 = Forces OP2# output to a logic 1 (default).
Logic 1 = Forces OP2# output to a logic 0.
MCR[4]: Internal Loopback Enable
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loop-
back section and Figure 13.
MCR[5]: Xon-Any Enable
Logic 0 = Disable Xon-Any function (for 16C550
compatibility, default).
Logic 1 = Enable Xon-Any function. In this mode,
any RX character received will resume transmit
operation. The RX character will be loaded into the
RX FIFO , unless the RX character is an Xon or
Xoff character and the 2852 is programmed to use
the Xon/Xoff flow control.
MCR[6]: Infrared Encoder/Decoder Enable
Logic 0 = Enable the standard modem receive and
transmit input/output interface. (Default)
Logic 1 = Enable infrared IrDA receive and transmit
inputs/outputs. The TX/RX output/input are routed
to the infrared encoder/decoder. The data input and
output levels conform to the IrDA infrared interface
requirement. While in this mode, the infrared TX
output will be a logic 0 during idle data conditions.
MCR[7]: Clock Prescaler Select
Logic 0 = Divide by one. The input clock from the
crystal or external clock is fed directly to the Pro-
grammable Baud Rate Generator without further
modification, i.e., divide by one (default).
Logic 1 = Divide by four. The prescaler divides the
input clock from the crystal or external clock by four
and feeds it to the Programmable Baud Rate Gen-
erator, hence, data rates become one forth.
4.10 L
INE
S
TATUS
R
EGISTER
(LSR) - R
EAD
O
NLY
This register provides the status of data transfers be-
tween the UART and the host.
LSR[0]: Receive Data Ready Indicator
Logic 0 = No data in receive holding register or
FIFO (default).
Logic 1 = Data has been received and is saved in
the receive holding register or FIFO.
LSR[1]: Receiver Overrun Flag
Logic 0 = No overrun error. (default)
Logic 1 = Overrun error. A data overrun error condi-
tion occurred in the receive shift register. This hap-
pens when additional data arrives while the FIFO is
full. In this case the previous data in the receive
shift register is overwritten. Note that under this
condition the data byte in the receive shift register
is not transferred into the FIFO, therefore the data
in the FIFO is not corrupted by the error.
LSR[2]: Receive Data Parity Error Flag
Logic 0 = No parity error (default).
Logic 1 = Parity error. The receive character in RHR
does not have correct parity information and is sus-
pect. This error is associated with the character
available for reading in RHR.
LSR[3]: Receive Data Framing Error Flag
Logic 0 = No framing error (default).
Logic 1 = Framing error. The receive character did
not have a valid stop bit(s). This error is associated
with the character available for reading in RHR.
LSR[4]: Receive Break Flag
Logic 0 = No break condition (default).
Logic 1 = The receiver received a break signal (RX
was a logic 0 for at least one character frame time).
In the FIFO mode, only one break character is
loaded into the FIFO. The break indication remains
until the RX input returns to the idle condition,
“mark” or logic 1.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indi-
cator. The THR bit is set to a logic 1 when the last da-
ta byte is transferred from the transmit holding regis-
ter to the transmit shift register. The bit is reset to log-
ic 0 concurrently with the data loading to the transmit
holding register by the host. In the FIFO mode this bit
is set when the transmit FIFO is empty, it is cleared
when the transmit FIFO contains at least 1 byte.
LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter
goes idle. It is set to logic 0 whenever either the THR
or TSR contains a data character. In the FIFO mode
this bit is set to a logic 1 whenever the transmit FIFO
and transmit shift register are both empty.
相關PDF資料
PDF描述
XR16C2852IJ 3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C850CJ UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control
XR16C850CM UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control
XR16C850CP UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control
XR16C850CQ UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control
相關代理商/技術參數(shù)
參數(shù)描述
XR16C2852CJ-0A-EB 功能描述:UART 接口集成電路 Supports C2852 44 ld PLCC, ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16C2852CJ-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16C2852CJTR-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16C2852IJ 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述:
XR16C2852IJ-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*