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參數(shù)資料
| 型號(hào)： | XR16C2852CJ |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| 中文描述： | 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 11/42頁 |
| 文件大?。?/td> | 574K |
| 代理商： | XR16C2852CJ |
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XR16C2852
REV. 2.0.0
3.3V AND 5V DUART WITH 128-BYTE FIFO
á
11
2.11.3 Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 128
bytes of transmit data. The THR empty flag (LSR bit-
5) is set whenever the FIFO is empty. The THR empty
flag can generate a transmit empty interrupt (ISR bit-
1) when the amount of data in the FIFO falls below its
programmed trigger level. The transmit empty inter-
rupt is enabled by IER bit-1. The TSR flag (LSR bit-6)
is set when TSR/FIFO becomes empty.
2.12 R
ECEIVER
The receiver section contains an 8-bit Receive Shift
Register (RSR) and 128 bytes of FIFO which includes
a byte-wide Receive Holding Register (RHR). The
RSR uses the 16X for timing. It verifies and validates
every bit on the incoming character in the middle of
each data bit. On the falling edge of a start or false
start bit, an internal receiver counter starts counting
at the 16X. After 8 clocks the start bit period should
be at the center of the start bit. At this time the start
bit is sampled and if it is still a logic 0 it is validated.
Evaluating the start bit in this manner prevents the re-
ceiver from assembling a false character. The rest of
the data bits and stop bits are sampled and validated
in this same manner to prevent false framing. If there
were any error(s), they are reported in the LSR regis-
ter bits 2-4. Upon unloading the receive data byte
from RHR, the receive FIFO pointer is bumped and
the error tags are immediately updated to reflect the
status of the data byte in RHR register. RHR can gen-
erate a receive data ready interrupt upon receiving a
character or delay until it reaches the FIFO trigger
level. Furthermore, data delivery to the host is guar-
anteed by a receive data ready time-out interrupt
when data is not received for 4 word lengths as de-
fined by LCR[1,0] plus 12 bits time. This is equivalent
to 3.7-4.6 character times. The RHR interrupt is en-
abled by IER bit-0.
F
IGURE
7. T
RANSMITTER
O
PERATION
IN
NON
-FIFO M
ODE
Transmit
Holding
Register
(THR)
Transmit Shift Register (TSR)
Data
Byte
L
S
B
M
S
B
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
TXNOFIFO1
16X
Clock
F
IGURE
8. T
RANSMITTER
O
PERATION
IN
FIFO
AND
F
LOW
C
ONTROL
M
ODE
Transmit Data Shift Register
(TSR)
Transmit
Data Byte
THR Interrupt (ISR bit-1) falls
below the programmed Trigger
Level and then when becomes
empty. FIFO is Enabled by FCR
bit-0=1
Transmit
FIFO
16X Clock
Auto CTS Flow Control (CTS# pin)
Auto Software Flow Control
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.
TXFIFO1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| XR16C2852CJ-0A-EB | 功能描述:UART 接口集成電路 Supports C2852 44 ld PLCC, ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C2852CJ-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C2852CJTR-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C2852IJ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| XR16C2852IJ-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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