REV. 2.1.3 14 2.11 Receiver The receiver section contains an 8-bit Recei" />
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REV. 2.1.3
14
2.11
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 128 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X/8X clock (CLK8/16 pin) for timing. It
verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of
a start or false start bit, an internal receiver counter starts counting at the 16X/8X clock rate. After 8 clocks (or
4 if 8X) the start bit period should be at the center of the start bit. At this time the start bit is sampled and if it is
still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false
character. The rest of the data bits and stop bits are sampled and validated in this same manner to prevent
false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon unloading the
receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are immediately updated to
reflect the status of the data byte in RHR register. RHR can generate a receive data ready interrupt upon
receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data delivery to the host is
guaranteed by a receive data ready time-out interrupt when data is not received for 4 word lengths as defined
by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by
IER bit-0.
2.11.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 128 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO1
16X or 8X
Clock
Receive Data Characters
Data Bit
Validation
Error
Tags in
LSR bits
4:2
鐩搁棞(gu膩n)PDF璩囨枡
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XR16C2850IP 鍒堕€犲晢:EXAR 鍒堕€犲晢鍏ㄧū:EXAR 鍔熻兘鎻忚堪:DUAL UART WITH 128-byte FIFO鈥檚 AND RS-485 HALF DUPLEX CONTROL
XR16C2850IP40 鍒堕€犲晢:EXAR 鍒堕€犲晢鍏ㄧū:EXAR 鍔熻兘鎻忚堪:3.3V AND 5V DUART WITH 128-BYTE FIFO
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