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| 型號(hào)： | XQ2V6000-4CG717N |
| 廠商： | Xilinx, Inc. |
| 英文描述： | QPro Virtex-II 1.5V Military QML Platform FPGAs |
| 中文描述： | QPro的Virtex - II 1.5V的軍事QML第平臺(tái)FPGA |
| 文件頁(yè)數(shù)： | 20/128頁(yè) |
| 文件大?。?/td> | 2738K |
| 代理商： | XQ2V6000-4CG717N |
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QPro Virtex-II 1.5V Military QML Platform FPGAs
20
www.xilinx.com
1-800-255-7778
DS122 (v1.1) January 7, 2004
Product Specification
R
The set and reset functionality of a register or a latch can be
configured as follows:
No set or reset
Synchronous set
Synchronous reset
Synchronous set and reset
Asynchronous set (preset)
Asynchronous reset (clear)
Asynchronous set and reset (preset and clear)
The synchronous reset has precedence over a set, and an
asynchronous clear has precedence over a preset.
Distributed SelectRAM Memory
Each function generator (LUT) can implement a 16 x 1-bit
synchronous RAM resource called a distributed SelectRAM
element. The SelectRAM elements are configurable within
a CLB
to implement the following:
Single-Port 16 x 8 bit RAM
Single-Port 32 x 4 bit RAM
Single-Port 64 x 2 bit RAM
Single-Port 128 x 1 bit RAM
Distributed SelectRAM memory modules are synchronous
(write) resources. The combinatorial read access time is
extremely fast, while the synchronous write simplifies
high-speed designs. A synchronous read can be imple-
mented with a storage element in the same slice. The dis-
tributed SelectRAM memory and the storage element share
the same clock input. A Write Enable (WE) input is active
High, and is driven by the SR input.
Table 13
shows the number of LUTs (2 per slice) occupied
by each distributed SelectRAM configuration.
Dual-Port 16 x 4 bit RAM
Dual-Port 32 x 2 bit RAM
Dual-Port 64 x 1 bit RAM
For single-port configurations, distributed SelectRAM mem-
ory has one address port for synchronous writes and asyn-
chronous reads.
For dual-port configurations, distributed SelectRAM mem-
ory has one port for synchronous writes and asynchronous
reads and another port for asynchronous reads. The func-
tion generator (LUT) has separated read address inputs
(A1, A2, A3, A4) and write address inputs (WG1/WF1,
WG2/WF2, WG3/WF3, WG4/WF4).
In single-port mode, read and write addresses share the
same address bus. In dual-port mode, one function genera-
tor (R/W port) is connected with shared read and write
addresses. The second function generator has the A inputs
(read) connected to the second read-only port address and
the W inputs (write) shared with the first read/write port
address.
Figure 18:
Register/Latch Configuration in a Slice
FF
LATCH
FFY
SR REV
D
Q
CE
CK
YQ
FF
LATCH
FFX
SR REV
D
Q
CE
CK
XQ
CE
DX
DY
BY
CLK
BX
SR
Attribute
INIT1
INIT0
SRHIGH
SRLOW
Attribute
INIT1
INIT0
SRHIGH
SRLOW
Reset Type
SYNC
ASYNC
DS031_22_110600
Table 13:
Distributed SelectRAM Configurations
RAM
Number of LUTs
16 x 1S
1
16 x 1D
2
32 x 1S
2
32 x 1D
4
64 x 1S
4
64 x 1D
8
128 x 1S
8
Notes:
1.
S = single-port configuration, and D = dual-port
configuration.
ds122_1_1.fm Page 20 Wednesday, January 7, 2004 9:15 PM
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PDF描述 |
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| XQ2V6000-4FG456M | QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V6000-4FG456N | QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ4005EX-4CB191N | QML High-Reliability FPGAs |
| XQ4005EX-3CB191M | QML High-Reliability FPGAs |
| XQ4005EX-3CB191N | QML High-Reliability FPGAs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XQ2V6000-4EF1152I | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Platform FPGAs |
| XQ2V6000-4FG456M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V6000-4FG456N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V6000-5EF1152I | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Platform FPGAs |
| XQ2V6000-5EF957I | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Platform FPGAs |
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