參數(shù)資料
型號： XQ2V6000-4CG717M
廠商： Xilinx, Inc.
英文描述： QPro Virtex-II 1.5V Military QML Platform FPGAs
中文描述： QPro的Virtex - II 1.5V的軍事QML第平臺FPGA
文件頁數(shù)： 76/128頁
文件大?。?/td> 2738K
代理商： XQ2V6000-4CG717M
QPro Virtex-II 1.5V Military QML Platform FPGAs
76
www.xilinx.com
1-800-255-7778
DS122 (v1.1) January 7, 2004
Product Specification
R
Pin Definitions
Table 74
provides a description of each pin type listed in QPro Virtex-II pinout tables.
Table 74:
QPro Virtex-II Pin Definitions
Pin Name
Direction
Description
User I/O Pins
IO_LXXY_#
Input/Output
All user I/O pins are capable of differential signalling and can implement LVDS, ULVDS,
BLVDS, LVPECL, or LDT pairs. Each user I/O is labeled “
IO_LXXY_#
”, where:
IO
indicates a user I/O pin.
LXXY
indicates a differential pair, with
XX
a unique pair in the bank and
Y = P/N
for the positive and negative sides of the differential pair.
#
indicates the bank number (0 through 7).
Dual-Function Pins
IO_LXXY_#/ZZZ
The dual-function pins are labelled “
IO_LXXY_#/ZZZ
”, where
ZZZ
can be one of the
following pins:
Per Bank -
VRP, VRN,
or
VREF
Globally -
GCLKX(S/P), BUSY/DOUT, INIT_B, DIN/D0 – D7, RDWR_B,
or
CS_B
With /ZZZ
DIN/D0, D1, D2,
D3, D4, D5, D6,
D7
Input/Output
In SelectMAP mode, D0 through D7 are configuration data pins. These pins become
user I/Os after configuration, unless the SelectMAP port is retained.
In bit-serial modes, DIN (D0) is the single-data input. This pin becomes a user I/O after
configuration.
CS_B
Input
In SelectMAP mode, this is the active-Low Chip Select signal. This pin becomes a user
I/O after configuration, unless the
SelectMAP port is retained.
RDWR_B
Input
In SelectMAP mode, this is the active-Low Write Enable signal. This pin becomes a
user I/O after configuration, unless the SelectMAP port is retained.
BUSY/DOUT
Output
In SelectMAP mode, BUSY controls the rate at which configuration data is loaded. This
pin becomes a user I/O after configuration, unless the SelectMAP port is retained.
In bit-serial modes, DOUT provides preamble and configuration data to downstream
devices in a daisy chain. This pin becomes a user I/O after configuration.
INIT_B
Bidirectional
(open-drain)
When Low, this pin indicates that the configuration memory is being cleared. When held
Low, the start of configuration is delayed. During configuration, a Low on this output
indicates that a configuration data error has occurred. This pin becomes a user I/O after
configuration.
GCLKx (S/P)
Input/Output
These are clock input pins that connect to Global Clock Buffers. These pins become
regular user I/Os when not needed for clocks.
VRP
Input
This pin is for the DCI voltage reference resistor of the P transistor (per bank).
VRN
Input
This pin is for the DCI voltage reference resistor of the N transistor (per bank).
ALT_VRP
Input
This is the alternative pin for the DCI voltage reference resistor of the P transistor.
ALT_VRN
Input
This is the alternative pin for the DCI voltage reference resistor of the N transistor.
V
REF
Input
These are input threshold voltage pins. They become user I/Os when an external
threshold voltage is not needed (per bank).
Dedicated Pins
(1)
CCLK
Input/Output
Configuration clock. Output in Master mode or Input in Slave mode.
ds122_1_1.fm Page 76 Wednesday, January 7, 2004 9:15 PM
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