參數(shù)資料
型號： XQ2V6000-4BG728N
廠商： Xilinx, Inc.
英文描述： QPro Virtex-II 1.5V Military QML Platform FPGAs
中文描述： QPro的Virtex - II 1.5V的軍事QML第平臺FPGA
文件頁數(shù)： 52/128頁
文件大?。?/td> 2738K
代理商： XQ2V6000-4BG728N
QPro Virtex-II 1.5V Military QML Platform FPGAs
52
www.xilinx.com
1-800-255-7778
DS122 (v1.1) January 7, 2004
Product Specification
R
IOB
Input Switching Characteristics
Input delays associated with the pad are specified for
LVTTL levels. For other standards, adjust the delays with
the values shown in
IOB Input Switching Characteristics
Standard Adjustments
, page 53
.
Table 42:
IOB Input Switching Characteristics
Description
Symbol
Device
Min
Max
Units
Propagation Delays
Pad to I output, no delay
T
IOPI
All
-
0.88
ns
Pad to I output, with delay
T
IOPID
XQ2V1000
-
2.43
ns
XQ2V3000
-
2.49
ns
XQ2V6000
-
2.66
ns
Propagation Delays
Pad to output IQ via transparent latch, no delay
T
IOPLI
All
-
1.05
ns
Pad to output IQ via transparent latch, with delay
T
IOPLID
XQ2V1000
-
4.09
ns
XQ2V3000
-
4.20
ns
XQ2V6000
-
4.55
ns
Clock CLK to output IQ
T
IOCKIQ
All
-
0.77
ns
Setup and Hold Times with Respect to Clock at IOB Input Register
Pad, no delay
T
IOPICK
/T
IOICKP
All
1.06/–0.45
-
ns
Pad, with delay
T
IOPICKD
/T
IOICK
PD
XQ2V1000
4.10/–2.58
-
ns
XQ2V3000
4.22/–2.66
-
ns
XQ2V6000
4.56/–2.90
-
ns
ICE input
T
IOICECK
/T
IOCKI
CE
All
0.24/ 0.04
-
ns
SR input (IFF, synchronous)
T
IOSRCKI
All
0.34
-
ns
Set/Reset Delays
SR input to IQ (asynchronous)
T
IOSRIQ
All
1.40
ns
GSR to output IQ
T
GSRQ
All
6.88
ns
Notes:
1.
Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see
Table 46
.
ds122_1_1.fm Page 52 Wednesday, January 7, 2004 9:15 PM
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